LSPC-A0: Difference between revisions
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[[File:Mvs_lspc-a0.jpg|right|thumb|LSPC-A0 graphics chip found in on a MV4.]] | [[File:Mvs_lspc-a0.jpg|right|thumb|LSPC-A0 graphics chip found in on a MV4.]] | ||
Part of the first generation [[GPU]], see | Part of the first generation [[GPU]], see {{Chipname|LSPC2-A2}} for more details. | ||
=Pinout= | |||
117: 8 ULN2803 K11 / 112 C0 | |||
116: C0 109 | 116: C0 109 | ||
115: C0 110 | 115: C0 110 | ||
124: 2H1 | 124: 2H1 | ||
125: CA4 | 125: CA4 | ||
| Line 15: | Line 13: | ||
127: C0 37/1 Ls273 E4/5 | 127: C0 37/1 Ls273 E4/5 | ||
128: C0 54/B0 21 | 128: C0 54/B0 21 | ||
158: 3 D7 (AS04) | 158: 3 D7 (AS04) | ||
| Line 23: | Line 20: | ||
OpenOffice Draw file: [[File:lspc-a0.odg]] | OpenOffice Draw file: [[File:lspc-a0.odg]] | ||
*A1~A3: | *A1~A3: {{Chipname|68k}} address bus | ||
*D0~D15: | *D0~D15: 68k data bus | ||
*SVA0~SVA14: Slow VRAM bank address bus | *SVA0~SVA14: Slow VRAM bank address bus | ||
*SVD0~SVD15: Slow VRAM bank data bus | *SVD0~SVD15: Slow VRAM bank data bus | ||
*FVA0~FVA10: Fast VRAM bank address bus | *FVA0~FVA10: Fast VRAM bank address bus | ||
*FVD0~FVD15: Fast VRAM bank data bus | *FVD0~FVD15: Fast VRAM bank data bus | ||
*LOA0~LOA15: | *LOA0~LOA15: {{Chipname|LO ROM}} address bus ([[P bus]] ?) | ||
[[Category:Chips]] | [[Category:Chips]] | ||
Revision as of 02:38, 16 January 2016
Part of the first generation GPU, see LSPC2-A2 for more details.
Pinout
117: 8 ULN2803 K11 / 112 C0 116: C0 109 115: C0 110 124: 2H1 125: CA4 126: F7 LS86 12 127: C0 37/1 Ls273 E4/5 128: C0 54/B0 21 158: 3 D7 (AS04)
(Max size:File:lspc-a0_pinout.png)
File:Lspc-a0 pinout.png
OpenOffice Draw file: File:Lspc-a0.odg