Revision as of 19:17, 13 August 2012

MVS specific chip that does a bunch of unrelated things.

Why is A3 needed ?

Pinout

OpenOffice Draw file: File:Neo-i0.odg

A0~A3,A7: 68k address bus
P0~P15: GPU multiplexed bus
Q00~Q18: SFIX ROM address lines
SM1CS(ORO0): SM1 ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1)
SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?)
Q21, Q22: METER1, METER2
Q23, Q24: LOCK1, LOCK2
DS0, DS1: Data select for 2-slot systems made from SLOT0, SLOT1, PORTADRS and ROMOE, goes to a NEO-G0
CUNTOUT: Address decode from NEO-F0

@@ Line 3: / Line 3: @@
 MVS specific chip that does a bunch of unrelated things.
-*[[S ROM]] address latch for [[SFIX]], same as S ROM portion of [[NEO-273]]
+*[[S ROM]] 16bit address latch for [[SFIX]], same as S ROM portion of [[NEO-273]]
-*[[SM1]] /CS output when Z80 is reading from ROM and SM1/SFIX is enabled (SM1CS = SDROM OR SYSTEM)
+*[[SM1]] /CS output when Z80 is reading from ROM and onboard ROMs are enabled
-*/ROMOE output for cartridge [[PROG board]] (ROMOE = ROMOEU AND ROMEOU)
+*/ROMOE output for cartridge(s) [[PROG board]]
-*Video sync output for JAMMA edge
+*Video sync inversion (or not) to JAMMA edge
 *Coin counter and coin lockout output
+Why is A3 needed ?
 =Pinout=
-[[File:Neo-i0_pinout.png]]
+{|
+|
+[[File:Neo-i0_pinout.png|512px]]
 OpenOffice Draw file: [[File:neo-i0.odg]]
-*P0~P15: [[GPU]] multiplexed bus.
+|
+*A0~A3,A7: [[68k]] address bus
-On a MV1F:
+*P0~P15: [[GPU]] multiplexed bus
-*Q00~Q18 are connected to the [[SFIX]] ROM address lines.
+*Q00~Q18: [[SFIX]] ROM address lines
-*SM1CS(ORO0) = SYSTEM(ORI0) OR SDROM(ORI1)
+*SM1CS(ORO0): [[SM1]] ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1)
-*SYNCOUT = SYNCIN XOR SYNCREV ?
+*SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?)
 *Q21, Q22: METER1, METER2
 *Q23, Q24: LOCK1, LOCK2
+*DS0, DS1: Data select for 2-slot systems made from SLOT0, SLOT1, PORTADRS and ROMOE, goes to a [[NEO-G0]]
+*CUNTOUT: Address decode from [[NEO-F0]]
+|}
 [[Category:Chips]]