LSPC-A0: Difference between revisions
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Part of the first generation [[GPU]], see [[LSPC2-A2]] for more details. | Part of the first generation [[GPU]], see [[LSPC2-A2]] for more details. | ||
116: C0 109 | |||
115: C0 110 | |||
==Pinout== | ==Pinout== |
Revision as of 15:50, 19 August 2012
Part of the first generation GPU, see LSPC2-A2 for more details.
116: C0 109 115: C0 110
Pinout
117: 8 ULN2803 K11 / 112 C0
126: F7 LS86 12
127: C0 37/1 Ls273 E4/5
128: C0 54/B0 21
158: 3 D7 (AS04)
(Max size:File:lspc-a0_pinout.png)
File:Lspc-a0 pinout.png
OpenOffice Draw file: File:Lspc-a0.odg
- A1~A3: 68k address bus
- D0~D15: 68k data bus
- SVA0~SVA14: Slow VRAM bank address bus
- SVD0~SVD15: Slow VRAM bank data bus
- FVA0~FVA10: Fast VRAM bank address bus
- FVD0~FVD15: Fast VRAM bank data bus
- LOA0~LOA15: LO ROM address bus (P bus ?)
- DOTA/DOTB,H,LOAD: C ROM multiplexer control, see PRO-CT0
- EVEN: Swap signal for dual pixel data
- IP0/IP1: