Timer interrupt: Difference between revisions
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[[68k vector table|Vector address]] on | [[68k vector table|Vector address]] on cartridge systems: $68. On CD systems: $64. | ||
This [[68k interrupts|interrupt]] is triggered when the | This [[68k interrupts|interrupt]] is triggered when the 32-bit down-counter internal to [[LSPC]] reaches 0. | ||
The value of this counter is decremented by the [[Clock|pixel clock]] (6MHz, every 166.7ns), and reloaded with the specified value in {{Reg|REG_TIMERHIGH}} and {{Reg|REG_TIMERLOW}} each time one of these 3 selectable events occur: | The value of this counter is decremented by the [[Clock|pixel clock]] (6MHz, every 166.7ns), and reloaded with the specified value in {{Reg|REG_TIMERHIGH}} and {{Reg|REG_TIMERLOW}} each time one of these 3 selectable events occur: | ||
* | *Just when REG_TIMERLOW register is written to (immediately). | ||
* At the beginning of the frame blanking period. | *At the beginning of the frame blanking period (one-shot). | ||
* When the counter reaches 0 (repeat). | *When the counter reaches 0 (repeat). | ||
Like the others, this interrupt needs to be acknowledged to trigger again. | |||
The {{Reg|REG_LSPCMODE}} | The {{Reg|REG_LSPCMODE}} register is used to configure the timer's operation: | ||
*Bit 7 = 1: Load counter when it becomes 0. | *Bit 7 = 1: Load counter when it becomes 0. | ||
*Bit 6 = 1: Load counter at the beginning of the | *Bit 6 = 1: Load counter at the beginning of the hblank of the first vblank line. | ||
*Bit 5 = 1: Load counter as soon as REG_TIMERLOW is written to. | *Bit 5 = 1: Load counter as soon as REG_TIMERLOW is written to. | ||
*Bit 4 = 1: Enable timer interrupt. | *Bit 4 = 1: Enable timer interrupt. | ||
If bit 5 is set | If bit 5 is set, either bit 6, 7 or both must also be set to 1. | ||
REG_TIMERHIGH and REG_TIMERLOW | When the timer interrupt is enabled, the value of REG_TIMERHIGH and REG_TIMERLOW should always be set higher than 2, or it may lock the program. | ||
To trigger interrupts for every N pixels, set the timer registers to N-1, and set bits 4 and 7 of REG_LSPCMODE. | To trigger interrupts for every N pixels, set the timer registers to N-1, and set bits 4 and 7 of REG_LSPCMODE. | ||
To trigger interrupts when | To trigger interrupts when rendering reaches multiple arbitrary display locations, set bits 4, 5 and 7 of REG_LSPCMODE. Then, in the interrupt handler routine, set the interval between the next interrupt and the following in the timer registers. | ||
[[Category:Base system]] | [[Category:Base system]] | ||
[[Category:Video system]] |
Revision as of 07:02, 16 January 2016
Vector address on cartridge systems: $68. On CD systems: $64.
This interrupt is triggered when the 32-bit down-counter internal to LSPC reaches 0. The value of this counter is decremented by the pixel clock (6MHz, every 166.7ns), and reloaded with the specified value in REG_TIMERHIGH and REG_TIMERLOW each time one of these 3 selectable events occur:
- Just when REG_TIMERLOW register is written to (immediately).
- At the beginning of the frame blanking period (one-shot).
- When the counter reaches 0 (repeat).
Like the others, this interrupt needs to be acknowledged to trigger again.
The REG_LSPCMODE register is used to configure the timer's operation:
- Bit 7 = 1: Load counter when it becomes 0.
- Bit 6 = 1: Load counter at the beginning of the hblank of the first vblank line.
- Bit 5 = 1: Load counter as soon as REG_TIMERLOW is written to.
- Bit 4 = 1: Enable timer interrupt.
If bit 5 is set, either bit 6, 7 or both must also be set to 1.
When the timer interrupt is enabled, the value of REG_TIMERHIGH and REG_TIMERLOW should always be set higher than 2, or it may lock the program.
To trigger interrupts for every N pixels, set the timer registers to N-1, and set bits 4 and 7 of REG_LSPCMODE.
To trigger interrupts when rendering reaches multiple arbitrary display locations, set bits 4, 5 and 7 of REG_LSPCMODE. Then, in the interrupt handler routine, set the interval between the next interrupt and the following in the timer registers.