Mode of operation
The value of this counter is decremented by the pixel clock (6MHz, every 166.7ns), and reloaded with the value specified in REG_TIMERHIGH and REG_TIMERLOW each time one of these 3 selectable events occur:
- Just when REG_TIMERLOW register is written to (immediately).
- At the beginning of the frame blanking period (one-shot).
- When the counter reaches 0 (repeat).
- Minimum time ($00000000): 166.7ns (1 pixel, useless)
- Maximum time ($FFFFFFFF): 715.8s (42366 frames, 11.9 minutes)
- Cartridge systems: $68 (IRQ2)
- CD systems: $64 (IRQ1)
Like the others, this interrupt needs to be acknowledged with REG_IRQACK to trigger again.
The REG_LSPCMODE register is used to configure the timer's operation:
- Bit 7 = 1: Reload counter when it reaches 0.
- Bit 6 = 1: Reload counter at the beginning of the hblank of the first vblank line (start of each frame).
- Bit 5 = 1: Reload counter as soon as REG_TIMERLOW is written to.
- Bit 4 = 1: Enable timer interrupt.
Note that if bit 5 is set, either bit 6, 7 or both must also be set to 1.
To trigger interrupts every N pixels, set the reload value to N-1. So 384-1 = $17F for exactly one scanline.
To trigger interrupts when rendering reaches multiple arbitrary display locations, set bits 4, 5 and 7 of REG_LSPCMODE. Then, in the interrupt handler routine, set the new interval between the next interrupt and the following.