Reset: Difference between revisions

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VCCON (MVS) or RST (AES reset button, PST518B) -> NEO-B1 -> RESET (rises slowly, open collector in B1 ?) -> LSPC -> RESETP.
The NeoGeo reset "signal path" can be confusing. The involved signals are {{Sig|VCCON|VCCON}} (MVS only) or {{Sig|RST|RST}} (AES reset button and [[PST518B]]), {{Sig|RESET|RESET}} (main, clean reset signal), and {{Sig|RESETP|RESETP}} (reset release pulse for {{Chipname|NEO-D0}}).


Notes:
==Path==


* VCCON/RST depends on power supply or user input (main reset signal)
The reset trigger starts with signals VCCON or RST, which come from either the reset button or the PST518B reset generator. It goes to {{Chipname|NEO-B1}}, which sets its internal [[watchdog]] timer to generate a long enough negative pulse on RESET. {{Chipname|LSPC2-A2}} synchronizes the rising edge to the main clock's falling edge to output a 1mclk negative pulse on RESETP.
* NEO-B1 ANDs it with the watchdog reset signal (internal), or simply resets the watchdog timer to force a watchdog reset as long as VCCON/RST is low ?
 
* LSPC generates RESETP, which is a 1mclk long negative pulse sync'd to mclk falling edge triggered when RESET rises (used to sync clocks in NEO-D0)
VCCON, RST and RESET seem to be open-collector lines. RESET is pulled high by a 4.7k resistor.


[[File:resets.png]]
[[File:resets.png]]
==Notes==


RESET might be synchronized with a clock reaching B1 (1MB ? 6MB ?).
RESET might be synchronized with a clock reaching B1 (1MB ? 6MB ?).

Revision as of 18:23, 22 June 2016

The NeoGeo reset "signal path" can be confusing. The involved signals are VCCON (MVS only) or RST (AES reset button and PST518B), RESET (main, clean reset signal), and RESETP (reset release pulse for NEO-D0).

Path

The reset trigger starts with signals VCCON or RST, which come from either the reset button or the PST518B reset generator. It goes to NEO-B1, which sets its internal watchdog timer to generate a long enough negative pulse on RESET. LSPC2-A2 synchronizes the rising edge to the main clock's falling edge to output a 1mclk negative pulse on RESETP.

VCCON, RST and RESET seem to be open-collector lines. RESET is pulled high by a 4.7k resistor.

Notes

RESET might be synchronized with a clock reaching B1 (1MB ? 6MB ?).

RESETP is triggered by the watchdog also (since it asserts RESET).