Reset: Difference between revisions
mNo edit summary |
mNo edit summary |
||
| Line 1: | Line 1: | ||
The NeoGeo reset "signal path" can be confusing. The involved signals are {{Sig|VCCON|VCCON}} (MVS only) or {{Sig|RST|RST}} (AES reset button and [[PST518B]]), {{Sig|RESET|RESET|N}} (main, clean reset signal), and {{Sig|RESETP|RESETP|N}} ( | The NeoGeo reset "signal path" can be confusing. The involved signals are {{Sig|VCCON|VCCON}} (MVS only) or {{Sig|RST|RST}} (AES reset button and [[PST518B]]), {{Sig|RESET|RESET|N}} (main, clean reset signal), and {{Sig|RESETP|RESETP|N}} (phase sync pulse for {{Chipname|NEO-D0}}). | ||
==Path== | ==Path== | ||
Revision as of 20:10, 28 April 2017
The NeoGeo reset "signal path" can be confusing. The involved signals are VCCON (MVS only) or RST (AES reset button and PST518B), RESET (main, clean reset signal), and RESETP (phase sync pulse for NEO-D0).
Path
The reset trigger starts with signals VCCON or RST, which come from either the reset button or the PST518B reset generator. It goes to NEO-B1, which sets its internal watchdog timer to generate a long enough negative pulse on RESET. LSPC2-A2 synchronizes the rising edge to the main clock's falling edge to output a 1mclk negative pulse on RESETP.
VCCON, RST and RESET seem to be open-collector lines. RESET is pulled high by a 4.7k resistor.
Notes
RESET might be synchronized with a clock reaching B1 (1MB ? 6MB ?).
RESETP is triggered by the watchdog also (since it asserts RESET).