NEO-G0: Difference between revisions
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=AES | =Pinouts= | ||
==AES== | |||
Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation. | Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation. | ||
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=MV2B | ==MV2B== | ||
< | <gallery> | ||
File:Neo-g0_J4_pinout.png|J4: 68k data bus access for both slots. DS0,DS1: Slot 68k data enables from [[NEO-I0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_J4.odg]] | |||
File:Neo-g0_J12_pinout.png|J12: ADPCM buses access for both slots. 10 AS04: negated /ROE from YM2610, 12 AS04: negated /POE from YM2610. SLOT0, SLOT1: enables from [[NEO-F0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_J12.odg]] | |||
File:Neo-g0_C7_pinout.png|B7: Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. 28 C0 (PAL ?):Palette RAM address decode from [[PRO-C0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_C7.odg]] | |||
</gallery> | |||
[[ | |||
OpenOffice Draw file: [[File:neo- | |||
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Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. | |||
[[Category:Chips]] | [[Category:Chips]] |
Revision as of 12:05, 24 March 2019
Package | QFP64R |
Manufacturer | |
First use | 1992 ? |
Used on | MV2B ... |
Quadruple 245 with additional OR and AND gates. Predecessor of NEO-BUF.
Internal logic
|
Pinouts
AES
Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.
|
MV2B
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J4: 68k data bus access for both slots. DS0,DS1: Slot 68k data enables from NEO-I0. OpenOffice Draw file: File:Neo-g0 mv2b J4.odg
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J12: ADPCM buses access for both slots. 10 AS04: negated /ROE from YM2610, 12 AS04: negated /POE from YM2610. SLOT0, SLOT1: enables from NEO-F0. OpenOffice Draw file: File:Neo-g0 mv2b J12.odg
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B7: Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. 28 C0 (PAL ?):Palette RAM address decode from PRO-C0. OpenOffice Draw file: File:Neo-g0 mv2b C7.odg