LSPC-A0: Difference between revisions

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=Pinout=
[[File:Mvs_lspc-a0.jpg|right|thumb|LSPC-A0 graphics chip found in on a MV4.]]
 
Part of the first generation [[GPU]], see [[LSPC2-A2]] for more details.
 
==Pinout==


1:VCC
2:A1
3:A2
4:A3
5:D0
6:D1
7:D2
8:D3
9:D4
10:D5
11:D6
12:D7
13:D8
14:D9
15:D10
16:D11
17:D12
18:D13
19:GND
20:VCC
21:GND
22:D14
23:D15
24:Slow VRAM A0
25:Slow VRAM A1
26:Slow VRAM A2
27:Slow VRAM A3
28:Slow VRAM A4
29:Slow VRAM A5
30:Slow VRAM A6
31:Slow VRAM A7
32:Slow VRAM A8
33:Slow VRAM A9
34:Slow VRAM A10
35:Slow VRAM A11
36:Slow VRAM A12
37:Slow VRAM A13
38:Slow VRAM A14
39:Slow VRAM D0 (K9)
40:VCC
41:GND
42:GND
43:Slow VRAM D1
44:Slow VRAM D2
45:Slow VRAM D3
46:Slow VRAM D4
47:Slow VRAM D5
48:Slow VRAM D6
49:Slow VRAM D7
50:Slow VRAM D0 (L9)
51:Slow VRAM D1
52:Slow VRAM D2
53:Slow VRAM D3
54:Slow VRAM D4
55:Slow VRAM D5
56:Slow VRAM D6
57:Slow VRAM D7
58:Slow VRAM /OE
59:Slow VRAM /RW
60: 4
61: 3
62: BR2
63: 1
64: 2
65: 3
66: 4
67: TR5 5814 bot
68: 4
69: 3
70: BR2
71: 1
72: 2
73: 3
74: 4
75: TR5 5814 top
76: TL4 5814
77: 8RB 68k
78: 9RB 68k
79: GND
80: GND
81: VCC
82: A0 LO
83: A1 LO
84: A2 LO
85: A3 LO
86: A4 LO
87: A5 LO
88: A6 LO
89: A7 LO
90: A8 LO
91: A9 LO
92: A10 LO
93: A11 LO
94: A12 LO
95: A13 LO
96: A14 LO
97: A15 LO
98: 18 N9
99: VCC
100: GND
101: VCC
102: 3 N9
103: 4 N9
104: 7 N9
105: 5 N10
106: 16 N10
107: 3 N10
108: 6 P10
109: 20 PRO-B0
110: 37 B0
111: 1 N10
112: 6 Z80
113: 9 LS161 B5
114: LOAD
115: 109
116: 110 C0
117: 8 ULN2803 K11 / 112 C0
117: 8 ULN2803 K11 / 112 C0
118: H
119: Even
120: VCC


121: GND
122: GND
123: C0 50
124: 17 R10
125: 2 R10
126: F7 LS86 12
126: F7 LS86 12
127: C0 37/1 Ls273 E4/5
127: C0 37/1 Ls273 E4/5
128: C0 54/B0 21
128: C0 54/B0 21
129: C0 121
 
130: C0 122
131: C0 124
132: C0 125
133: C0 105
134: C0 106
135: C0 107
136: C0 108
137: C0 123
138: PRO C0 126
139: 8
140: 7
141: 6
142: 5
143: 4
144: 3
145: 2
146: 1n
147: 2
148: 3
149: topleft fastram 6
150: GND
151: DOTA
152: DOTB
153: GND
154: C0 23
155: C0 18
156: 2 P10
157: 17 P10
158: 3 D7 (AS04)
158: 3 D7 (AS04)
159: GND
 
160: GND
(Max size:[[:File:lspc-a0_pinout.png]])<br>
[[File:lspc-a0_pinout.png|640px]]
 
OpenOffice Draw file: [[File:lspc-a0.odg]]
 
*A1~A3: [[68k]] address bus
*D0~D15: [[68k]] data bus
*SVA0~SVA14: Slow VRAM bank address bus
*SVD0~SVD15: Slow VRAM bank data bus
*FVA0~FVA10: Fast VRAM bank address bus
*FVD0~FVD15: Fast VRAM bank data bus
*LOA0~LOA15: [[LO ROM]] address bus ([[P bus]] ?)
*DOTA/DOTB,H,LOAD: C ROM multiplexer control, see [[PRO-CT0]]
*EVEN: Swap signal for dual pixel data
*IP0/IP1:


[[Category:Chips]]
[[Category:Chips]]

Revision as of 00:28, 4 August 2012

LSPC-A0 graphics chip found in on a MV4.

Part of the first generation GPU, see LSPC2-A2 for more details.

Pinout

117: 8 ULN2803 K11 / 112 C0

126: F7 LS86 12

127: C0 37/1 Ls273 E4/5

128: C0 54/B0 21

158: 3 D7 (AS04)

(Max size:File:lspc-a0_pinout.png)
File:Lspc-a0 pinout.png

OpenOffice Draw file: File:Lspc-a0.odg

  • A1~A3: 68k address bus
  • D0~D15: 68k data bus
  • SVA0~SVA14: Slow VRAM bank address bus
  • SVD0~SVD15: Slow VRAM bank data bus
  • FVA0~FVA10: Fast VRAM bank address bus
  • FVD0~FVD15: Fast VRAM bank data bus
  • LOA0~LOA15: LO ROM address bus (P bus ?)
  • DOTA/DOTB,H,LOAD: C ROM multiplexer control, see PRO-CT0
  • EVEN: Swap signal for dual pixel data
  • IP0/IP1:
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