Timer interrupt: Difference between revisions

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[[68k vector table|Vector address]] on cartridge systems: $68. On CD systems: $64.
The timer interrupt is a [[68k interrupts|68k interrupt]] triggered when the 32-bit down-counter internal to [[LSPC]] reaches 0. As it is synchronous with the video output, it is mainly used for [[scanline effects]].


This [[68k interrupts|interrupt]] can be used for [[scanline effects]], it is triggered when the 32-bit down-counter internal to [[LSPC]] reaches 0.
=Mode of operation=
The value of this counter is decremented by the [[Clock|pixel clock]] (6MHz, every 166.7ns), and reloaded with the specified value in {{Reg|REG_TIMERHIGH}} and {{Reg|REG_TIMERLOW}} each time one of these 3 selectable events occur:


*Just when REG_TIMERLOW register is written to (immediately).
The value of this counter is decremented by the [[Clock|pixel clock]] (6MHz, every 166.7ns), and reloaded with the value specified in {{Reg|REG_TIMERHIGH}} and {{Reg|REG_TIMERLOW}} each time one of these 3 selectable events occur:
*At the beginning of the frame blanking period (one-shot).
*When the counter reaches 0 (repeat).


Like the others, this interrupt needs to be acknowledged to trigger again.
* Just when {{Reg|REG_TIMERLOW}} register is written to (immediately).
* At the beginning of the frame blanking period (one-shot).
* When the counter reaches 0 (repeat).
 
=Range=
 
* Minimum time ($00000000): 166.7ns (1 pixel, useless)
* Maximum time ($FFFFFFFF): 715.8s (42366 frames, 11.9 minutes)
 
=[[68k vector table|Vector address]]=
* Cartridge systems: $68 (IRQ2)
* CD systems: $64 (IRQ1)
 
Like the others, this interrupt needs to be acknowledged with {{Reg|REG_IRQACK}} to trigger again.
 
=Configuration=


The {{Reg|REG_LSPCMODE}} register is used to configure the timer's operation:
The {{Reg|REG_LSPCMODE}} register is used to configure the timer's operation:


*Bit 7 = 1: Load counter when it becomes 0.
* Bit 7 = 1: Reload counter when it reaches 0.
*Bit 6 = 1: Load counter at the beginning of the hblank of the first vblank line.
* Bit 6 = 1: Reload counter at the beginning of the hblank of the first vblank line (start of each frame).
*Bit 5 = 1: Load counter as soon as REG_TIMERLOW is written to.
* Bit 5 = 1: Reload counter as soon as {{Reg|REG_TIMERLOW}} is written to.
*Bit 4 = 1: Enable timer interrupt.
* Bit 4 = 1: Enable timer interrupt.
 
Note that if bit 5 is set, either bit 6, 7 or both must also be set to 1.


If bit 5 is set, either bit 6, 7 or both must also be set to 1.
'''Caution''': When the timer interrupt is enabled, the value of {{Reg|REG_TIMERHIGH}} and {{Reg|REG_TIMERLOW}} should always be set higher than 4, or the CPU will get flooded with interrupts and the program will lock up.


When the timer interrupt is enabled, the value of REG_TIMERHIGH and REG_TIMERLOW should always be set higher than 2, or it may lock the program.
=Examples=


To trigger interrupts for every N pixels, set the timer registers to N-1, and set bits 4 and 7 of REG_LSPCMODE.
To trigger interrupts every N pixels, set the reload value to N-1. So 384-1 = $17F for exactly one scanline.


To trigger interrupts when rendering reaches multiple arbitrary display locations, set bits 4, 5 and 7 of REG_LSPCMODE. Then, in the interrupt handler routine, set the interval between the next interrupt and the following in the timer registers.
To trigger interrupts when rendering reaches multiple arbitrary display locations, set bits 4, 5 and 7 of REG_LSPCMODE. Then, in the interrupt handler routine, set the new interval between the next interrupt and the following.


[[Category:Base system]]
[[Category:Base system]]
[[Category:Video system]]
[[Category:Video system]]

Revision as of 11:13, 23 October 2016

The timer interrupt is a 68k interrupt triggered when the 32-bit down-counter internal to LSPC reaches 0. As it is synchronous with the video output, it is mainly used for scanline effects.

Mode of operation

The value of this counter is decremented by the pixel clock (6MHz, every 166.7ns), and reloaded with the value specified in REG_TIMERHIGH and REG_TIMERLOW each time one of these 3 selectable events occur:

  • Just when REG_TIMERLOW register is written to (immediately).
  • At the beginning of the frame blanking period (one-shot).
  • When the counter reaches 0 (repeat).

Range

  • Minimum time ($00000000): 166.7ns (1 pixel, useless)
  • Maximum time ($FFFFFFFF): 715.8s (42366 frames, 11.9 minutes)

Vector address

  • Cartridge systems: $68 (IRQ2)
  • CD systems: $64 (IRQ1)

Like the others, this interrupt needs to be acknowledged with REG_IRQACK to trigger again.

Configuration

The REG_LSPCMODE register is used to configure the timer's operation:

  • Bit 7 = 1: Reload counter when it reaches 0.
  • Bit 6 = 1: Reload counter at the beginning of the hblank of the first vblank line (start of each frame).
  • Bit 5 = 1: Reload counter as soon as REG_TIMERLOW is written to.
  • Bit 4 = 1: Enable timer interrupt.

Note that if bit 5 is set, either bit 6, 7 or both must also be set to 1.

Caution: When the timer interrupt is enabled, the value of REG_TIMERHIGH and REG_TIMERLOW should always be set higher than 4, or the CPU will get flooded with interrupts and the program will lock up.

Examples

To trigger interrupts every N pixels, set the reload value to N-1. So 384-1 = $17F for exactly one scanline.

To trigger interrupts when rendering reaches multiple arbitrary display locations, set bits 4, 5 and 7 of REG_LSPCMODE. Then, in the interrupt handler routine, set the new interval between the next interrupt and the following.