Signals: Difference between revisions

From NeoGeo Development Wiki
Jump to navigation Jump to search
(Created page with "*6M, 12M, 24M: 6MHz, 12MHz, and 24MHz clock signals *4MB: 4MHz inverted signal *A1~A19: 68k address bus *D0~D15: 68k data bus *R/W: 68k Read/Write *AS: 68k /AS */ROMOEL: $...")
 
mNo edit summary
 
(23 intermediate revisions by 3 users not shown)
Line 1: Line 1:
*6M, 12M, 24M: 6MHz, 12MHz, and 24MHz clock signals
Most names come from the official [[schematics]].
*4MB: 4MHz inverted signal
 
*A1~A19: [[68k]] address bus
Some help to decipher the names:
*D0~D15: 68k data bus
* / means the signal is active low.
*R/W: 68k Read/Write
* OE means Output Enable.
*AS: 68k /AS
* U is used for Upper (even) byte.
*/ROMOEL: $000000-$0FFFFF ([[P ROM|P1 ROM]]) odd byte read
* L is used for Lower (odd) byte.
*/ROMOEU: $000000-$0FFFFF (P1 ROM) even byte read
* B as suffix often means the signal is inverted.
*/ROMOE: $000000-$0FFFFF (P1 ROM) read
 
*/PORTOEL: $200000-$2FFFFF (P2+ ROM/[[PRO-CT0|Security chip]]) odd byte read
 
*/PORTOEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte read
=[[Clock]]s=
*/PORTWEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte write
{| class="regdef"
*/PORTWEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte write
|'''Name'''
*/PORTADRS: $200000-$2FFFFF (P2+ ROM/Security chip) any access
|'''Description'''
*CR0~CR31: [[C ROM]]s data bus (2*16bits), holds data for one 8 pixels line
|'''Comes from'''
|'''Fault consequence'''
|-
|24M
|24MHz master clock
|{{Chipname|NEO-D0}}
|Nothing works, no video at all
|-
|12M
|12MHz clock (24/2) non-inverted
|{{Chipname|NEO-D0}}
|Bad graphics
|-
|8M
|8MHz clock (24/3) non-inverted
|{{Chipname|LSPC}}
|No sound
|-
|6MB
|6MHz clock (24/4) inverted
|{{Chipname|NEO-D0}}
|Black screen ?
|-
|4M
|4MHz clock (24/6) non-inverted
|{{Chipname|LSPC}}
|No sound
|-
|4MB
|4MHz clock (24/6) inverted
|{{Chipname|LSPC}} + inverter
|?
|-
|1MB
|'''3MHz''' (!) clock (24/8) inverted
|{{Chipname|NEO-D0}}
|?
|-
|68KCLK
|12MHz clock (24/2) non-inverted
|{{Chipname|NEO-D0}}
|[[Click of death]]
|-
|68KCLKB
|12MHz clock (24/2) inverted
|{{Chipname|NEO-D0}}
|Bad audio in games using {{Chipname|PCM}}
|}
 
=[[68k]] CPU=
{| class="regdef"
|'''Name'''
|'''Description'''
|'''Type'''
|'''Comes from'''
|'''Fault consequence'''
|-
|A1~A23
|[[68k]] address bus
|Address
|{{Chipname|68k}}
|Click of death
|-
|A22I,A23I
|Altered address lines for [[68k vector table]] swap
|Address
|{{Chipname|NEO-E0}}
|Probably click of death
|-
|/AS
|68k Address Strobe
|Control
|{{Chipname|68k}}
|Probably click of death
|-
|D0~D15
|68k data bus
|Data
|Multiple
|Click of death
|-
|/DTACK
|68k Data Transmit ACKnowledge (see [[wait cycle]])
|Control
|{{Chipname|NEO-C1}}
|Click of death
|-
|/PORTADRS
|$200000-$2FFFFF (P2 ROM/[[PRO-CT0|Security chip]]) any access
|Control
|{{Chipname|NEO-C1}}
|Game crashes, bad graphics
|-
|/PORTOEL
|$200000-$2FFFFF (P2 ROM/Security chip) odd byte read
|Control
|{{Chipname|NEO-C1}}
|Game crashes, bad graphics
|-
|/PORTOEU
|$200000-$2FFFFF (P2 ROM/Security chip) even byte read
|Control
|{{Chipname|NEO-C1}}
|Game crashes, bad graphics
|-
|/PORTWEL
|$200000-$2FFFFF (P2 ROM/Security chip) odd byte write
|Control
|{{Chipname|NEO-C1}}
|Game crashes, [[multiplayer]] comm. error
|-
|/PORTWEU
|$200000-$2FFFFF (P2 ROM/Security chip) even byte write
|Control
|{{Chipname|NEO-C1}}
|Game crashes, bad graphics
|-
|/PWAIT0, /PWAIT1
|Delay configuration for [[P ROM|P2 ROM]] reads, see [[wait cycle]]
|Control
|{{Chipname|NEO-C1}}
|Game crashes (very likely)
|-
|R/W
|68k Read/Write
|Control
|{{Chipname|68k}}
|Click of death
|-
|/ROMOE
|$000000-$0FFFFF ([[P ROM|P1 ROM]]) read
|Control
|{{Chipname|NEO-C1}} + AND
|Game doesn't start
|-
|/ROMOEL
|$000000-$0FFFFF (P1 ROM) odd byte read
|Control
|{{Chipname|NEO-C1}}
|Game doesn't start
|-
|/ROMOEU
|$000000-$0FFFFF (P1 ROM) even byte read
|Control
|{{Chipname|NEO-C1}}
|Game doesn't start
|-
|/ROMWAIT
|Add 1-cycle delay for P1 ROM reads
|Control
|{{Chipname|NEO-C1}}
|Game freezes (unlikely)
|-
|/SROMOE
|$C00000-$CFFFFF ([[System ROM]]) read
|Control
|{{Chipname|NEO-E0}}
|Click of death
|-
|/SROMOEL
|$C00000-$CFFFFF (System ROM) odd byte read
|Control
|{{Chipname|NEO-C1}}
|Click of death
|-
|/SROMOEU
|$C00000-$CFFFFF (System ROM) even byte read
|Control
|{{Chipname|NEO-C1}}
|Click of death
|-
|}
 
=Graphics=
{| class="regdef"
|'''Name'''
|'''Description'''
|'''Type'''
|'''Comes from'''
|'''Fault consequence'''
|-
|2H1
|[[S ROM]] A3
|Address
|{{Chipname|LSPC}}
|Bad fix graphics
|-
|CA4
|[[C ROM]]s A4
|Address
|{{Chipname|LSPC}}
|Bad sprite graphics
|-
|C* or CR0~CR31
|C ROMs data bus (2*16bits), data for one 8-pixels line
|Data
|{{Chipname|C ROM}}
|Bad sprite graphics
|-
|FIXD0~FIXD7
|[[Fix layer]] data bus, data for 2 pixels
|Data
|{{Chipname|S ROM}}
|[[Graphic glitches|Static vertical lines]], solid color screen
|-
|P0~P23
|Multiplexed [[P bus]]
|Muxed
|Multiple
|Garbled or absent graphics
|-
|PA0~PA11
|[[Palette RAM]] address bus
|Address
|{{Chipname|NEO-B1}}
|Bad colors, snow, black screen
|-
|PAL
|[[Palette RAM]] decode for [[68k]] access
|Control
|{{Chipname|NEO-C1}}
|Bad colors, snow, black screen
|-
|PCK1, PCK2
|Graphics rendering control
|Control
|{{Chipname|LSPC2-A2}}
|Bad graphics, solid colors, black screen
|-
|PCK1B, PCK2B
|Graphics rendering control
|Control
|AS04 inverters
|Bad graphics
|}
 
*PCK1B: Low 55ns, high 610 (1.5MHz) Clock to latch C ROM address from P0~P23 ([[NEO-273|mapping]]) on rising edge.
*PCK2B: Low 55ns, high 610 (1.5MHz) Clock to latch S ROM address from P0~P15 ([[NEO-273|mapping]]) on rising edge.
 
=Misc.=
{| class="regdef"
|'''Name'''
|'''Description'''
|'''Type'''
|'''Comes from'''
|'''Fault consequence'''
|-
|/DIPRD0
|$300000~$31FFFF odd byte reads
|Control
|{{Chipname|NEO-C1}}
|Can't read [[hardware DIPs]], test button state and system type. See {{Reg|REG_DIPSW}} and {{Reg|REG_SYSTYPE}}.
|-
|/DIPRD1
|$320000~$33FFFF odd byte reads
|Control
|{{Chipname|NEO-C1}}
|Coins aren't detected, RTC access problems. See {{Reg|REG_STATUS_A}}.
|-
|/BITW0
|$380000~$39FFFF odd byte writes
|Control
|{{Chipname|NEO-C1}}
|No [[Pinouts#Joypad_ports|joypad]] output control, memory card access problems, MVS slot selection problems, erratic credits displays and marquee control, RTC access problems, no [[coin counter]]s and [[coin lockout]]s control. See [[Memory mapped registers]].
|-
|/BITW1
|$3A0000~$3BFFFF odd byte writes
|Control
|{{Chipname|NEO-C1}}
|Spurious or impossible writes to [[Memory_mapped_registers#System_registers|system registers]].
|-
|/BITWD0
|$3A0000~$3BFFFF odd byte writes
|Control
|{{Chipname|NEO-F0}}
|No [[Pinouts#Joypad_ports|joypad]] output control, memory card access problems. See {{Reg|REG_POUTPUT}} and {{Reg|REG_CRDBANK}}. Depends on /BITW0.
|-
|BNK0~2
|[[Memory card]] bank selection
|Control
|{{Chipname|NEO-D0}}
|Access problems with big memory cards.
|}
 
*SYSTEM: low when onboard ROMs selected
*SYSTEMB: inverted SYSTEM
 
=[[Z80]] CPU=
 
*SDA0~SDA15 : [[Z80]] address bus
*SDD0~SDD7: Z80 data bus
 
=Sound=
 
*SDRAD0~SDRAD7: ADPCM-A ROM [[YM2610#Multiplexed bus|multiplexed bus]] (data/address)
*SDRAD0~SDRAD7: ADPCM-A ROM [[YM2610#Multiplexed bus|multiplexed bus]] (data/address)
*SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
*SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
*SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
*SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
*SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
*SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
*P0~P23: C ROM, [[S ROM]] and [[LO RON]] address bus (multiplexed)
*PCK1B: Clock to latch C ROM address from P0~P23 ([[NEO-273|mapping]]) on rising edge
*PCK2B: Clock to latch S ROM address from P0~P15 ([[NEO-273|mapping]]) on rising edge
*CA4: C ROM A4
*2H1: S ROM A3
*FIXD0~FIXD7: S ROM data bus


[[Category:Chips]]
[[Category:Chips]]
[[Category:Repairs]]

Latest revision as of 02:02, 12 November 2019

Most names come from the official schematics.

Some help to decipher the names:

  • / means the signal is active low.
  • OE means Output Enable.
  • U is used for Upper (even) byte.
  • L is used for Lower (odd) byte.
  • B as suffix often means the signal is inverted.


Clocks

Name Description Comes from Fault consequence
24M 24MHz master clock NEO-D0 Nothing works, no video at all
12M 12MHz clock (24/2) non-inverted NEO-D0 Bad graphics
8M 8MHz clock (24/3) non-inverted LSPC No sound
6MB 6MHz clock (24/4) inverted NEO-D0 Black screen ?
4M 4MHz clock (24/6) non-inverted LSPC No sound
4MB 4MHz clock (24/6) inverted LSPC + inverter ?
1MB 3MHz (!) clock (24/8) inverted NEO-D0 ?
68KCLK 12MHz clock (24/2) non-inverted NEO-D0 Click of death
68KCLKB 12MHz clock (24/2) inverted NEO-D0 Bad audio in games using PCM

68k CPU

Name Description Type Comes from Fault consequence
A1~A23 68k address bus Address 68k Click of death
A22I,A23I Altered address lines for 68k vector table swap Address NEO-E0 Probably click of death
/AS 68k Address Strobe Control 68k Probably click of death
D0~D15 68k data bus Data Multiple Click of death
/DTACK 68k Data Transmit ACKnowledge (see wait cycle) Control NEO-C1 Click of death
/PORTADRS $200000-$2FFFFF (P2 ROM/Security chip) any access Control NEO-C1 Game crashes, bad graphics
/PORTOEL $200000-$2FFFFF (P2 ROM/Security chip) odd byte read Control NEO-C1 Game crashes, bad graphics
/PORTOEU $200000-$2FFFFF (P2 ROM/Security chip) even byte read Control NEO-C1 Game crashes, bad graphics
/PORTWEL $200000-$2FFFFF (P2 ROM/Security chip) odd byte write Control NEO-C1 Game crashes, multiplayer comm. error
/PORTWEU $200000-$2FFFFF (P2 ROM/Security chip) even byte write Control NEO-C1 Game crashes, bad graphics
/PWAIT0, /PWAIT1 Delay configuration for P2 ROM reads, see wait cycle Control NEO-C1 Game crashes (very likely)
R/W 68k Read/Write Control 68k Click of death
/ROMOE $000000-$0FFFFF (P1 ROM) read Control NEO-C1 + AND Game doesn't start
/ROMOEL $000000-$0FFFFF (P1 ROM) odd byte read Control NEO-C1 Game doesn't start
/ROMOEU $000000-$0FFFFF (P1 ROM) even byte read Control NEO-C1 Game doesn't start
/ROMWAIT Add 1-cycle delay for P1 ROM reads Control NEO-C1 Game freezes (unlikely)
/SROMOE $C00000-$CFFFFF (System ROM) read Control NEO-E0 Click of death
/SROMOEL $C00000-$CFFFFF (System ROM) odd byte read Control NEO-C1 Click of death
/SROMOEU $C00000-$CFFFFF (System ROM) even byte read Control NEO-C1 Click of death

Graphics

Name Description Type Comes from Fault consequence
2H1 S ROM A3 Address LSPC Bad fix graphics
CA4 C ROMs A4 Address LSPC Bad sprite graphics
C* or CR0~CR31 C ROMs data bus (2*16bits), data for one 8-pixels line Data C ROM Bad sprite graphics
FIXD0~FIXD7 Fix layer data bus, data for 2 pixels Data S ROM Static vertical lines, solid color screen
P0~P23 Multiplexed P bus Muxed Multiple Garbled or absent graphics
PA0~PA11 Palette RAM address bus Address NEO-B1 Bad colors, snow, black screen
PAL Palette RAM decode for 68k access Control NEO-C1 Bad colors, snow, black screen
PCK1, PCK2 Graphics rendering control Control LSPC2-A2 Bad graphics, solid colors, black screen
PCK1B, PCK2B Graphics rendering control Control AS04 inverters Bad graphics
  • PCK1B: Low 55ns, high 610 (1.5MHz) Clock to latch C ROM address from P0~P23 (mapping) on rising edge.
  • PCK2B: Low 55ns, high 610 (1.5MHz) Clock to latch S ROM address from P0~P15 (mapping) on rising edge.

Misc.

Name Description Type Comes from Fault consequence
/DIPRD0 $300000~$31FFFF odd byte reads Control NEO-C1 Can't read hardware DIPs, test button state and system type. See REG_DIPSW and REG_SYSTYPE.
/DIPRD1 $320000~$33FFFF odd byte reads Control NEO-C1 Coins aren't detected, RTC access problems. See REG_STATUS_A.
/BITW0 $380000~$39FFFF odd byte writes Control NEO-C1 No joypad output control, memory card access problems, MVS slot selection problems, erratic credits displays and marquee control, RTC access problems, no coin counters and coin lockouts control. See Memory mapped registers.
/BITW1 $3A0000~$3BFFFF odd byte writes Control NEO-C1 Spurious or impossible writes to system registers.
/BITWD0 $3A0000~$3BFFFF odd byte writes Control NEO-F0 No joypad output control, memory card access problems. See REG_POUTPUT and REG_CRDBANK. Depends on /BITW0.
BNK0~2 Memory card bank selection Control NEO-D0 Access problems with big memory cards.
  • SYSTEM: low when onboard ROMs selected
  • SYSTEMB: inverted SYSTEM

Z80 CPU

  • SDA0~SDA15 : Z80 address bus
  • SDD0~SDD7: Z80 data bus

Sound

  • SDRAD0~SDRAD7: ADPCM-A ROM multiplexed bus (data/address)
  • SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
  • SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
  • SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
Retrieved from "https://wiki.neogeodev.org/index.php?title=Signals&oldid=6566"