Replacement chip: Difference between revisions

From NeoGeo Development Wiki
Jump to navigation Jump to search
mNo edit summary
mNo edit summary
 
Line 66: Line 66:
=Logic definitions=
=Logic definitions=


Use pin names instead of numbers ?
See https://github.com/neogeodev/SNKVerilog
 
==NEO-257==
 
Verified: NO.
 
<syntaxhighlight lang="verilog">
// TODO: Reverse order of bits/pins
assign {8,9,11,12,23,24,27,28} = (35&~18) ? 17 ? {5,7,14,16,20,22,30,32} : {4,6,13,15,19,21,29,31} : 8'bzzzzzzzz;
assign {40,41,43,44,55,56,59,60} = (35&(~(33|34))) ? 17 ? {36,38,45,47,51,53,62,64} : {37,39,46,48,52,54,63,1} : 8'bzzzzzzzz;
</syntaxhighlight>
 
==NEO-273==
 
Verified: NO.
 
<syntaxhighlight lang="verilog">
reg [19:0] C_LATCH;
reg [15:0] S_LATCH;
 
assign {46,45,44,43,41,40,39,38,14,13,12,11,9,8,7,6,33,32,1,64} = C_LATCH;
assign {37,36,35,34,18,17,16,15,5,4,3,2,51,50,49,48} = S_LATCH;
assign 47 = ~46;
 
always @(posedge 23)
  C_LATCH <= {27,25,59,57,55,54,53,52,31,30,29,28,22,21,20,19,63,62,61,60};
 
always @(posedge 24)
  S_LATCH <= {55,54,53,52,31,30,29,28,22,21,20,19,63,62,61,60};
</syntaxhighlight>
 
==NEO-BUF==
 
Verified: NO.
 
<syntaxhighlight lang="verilog">
// A0~7 <= B0~7
assign {32,33,34,35,37,38,39,40} = (44|45) ? 8'bzzzzzzzz : {5,4,3,2,1,48,47,46};
// A8~15 <= B8~15
assign {22,23,24,26,27,28,29,30} = (44|45) ? 8'bzzzzzzzz : {16,15,14,13,10,9,8,7};
// B0~7 <= A0~7
assign {5,4,3,2,1,48,47,46} = (44|(~45)) ? 8'bzzzzzzzz : {32,33,34,35,37,38,39,40};
// B8~15 <= A8~15
assign {16,15,14,13,10,9,8,7} = (44|(~45)) ? 8'bzzzzzzzz : {22,23,24,26,27,28,29,30};
</syntaxhighlight>
 
==NEO-C1==
 
Verified: Absolutely not.
 
<syntaxhighlight lang="verilog">
// Address decoding, is everything in sync with AS ?
assign ROMZONE = |{A23I,A22I,A21,A20};                  // 000000 0FFFFF
assign WRAMZONE = |{A23I,A22I,A21,~A20};                // 100000 1FFFFF
assign PORTZONE = |{A23I,A22I,~A21,A20};                // 200000 2FFFFF
assign CTRL1ZONE = |{A23I,A22I,~A21,~A20,A19,A18,A17};  // 300000 31FFFF
assign ICOMZONE = |{A23I,A22I,~A21,~A20,A19,A18,~A17};  // 320000 33FFFF
assign CTRL2ZONE = |{A23I,A22I,~A21,~A20,A19,~A18};      // 340000 37FFFF not sure if A17 is used (up to 35FFFF only ?)
assign BITW0 = |{A23I,A22I,~A21,~A20,~A19,A18,A17};      // 380000 39FFFF ?
assign BITW1 = |{A23I,A22I,~A21,~A20,~A19,A18,~A17};    // 3A0000 3BFFFF ?
assign LSPCZONE = |{A23I,A22I,~A21,~A20,~A19,~A18};      // 3C0000 3DFFFF not sure if A17 is used (up to 3DFFFF only ?)
assign PAL = |{A23I,~A22I};                              // 400000 7FFFFF
assign CARDZONE = |{~A23I,A22I};                        // 800000 BFFFFF
assign SROMZONE = |{~A23I,~A22I,A21,A20};                // C00000 CFFFFF
assign SRAMZONE = |{~A23I,~A22I,A21,~A20};              // D00000 DFFFFF
 
assign WORDACCSS = LDS|UDS;
 
assign ROMOEL = ~RW | LDS | ROMZONE;
assign ROMOEU = ~RW | UDS | ROMZONE;
assign PORTOEL = ~RW | LDS | PORTZONE;
assign PORTOEU = ~RW | UDS | PORTZONE;
assign PORTWEL = RW | LDS | PORTZONE;
assign PORTWEU = RW | UDS | PORTZONE;
assign PADRS = PORTZONE;
assign WRL = ~RW | LDS | WRAMZONE;
assign WRU = ~RW | UDS | WRAMZONE;
assign WWL = RW | LDS | WRAMZONE;
assign WWU = RW | UDS | WRAMZONE;
assign SROMOEL = ~RW | LDS | SROMZONE;
assign SROMOEU = ~RW | UDS | SROMZONE;
assign SRAMOEL = ~RW | LDS | SRAMZONE;
assign SRAMOEU = ~RW | UDS | SRAMZONE;
assign SRAMWEL = RW | LDS | SRAMZONE;
assign SRAMWEU = RW | UDS | SRAMZONE;
 
assign DIPRD0 = ? // Asks NEO-F0 for dipswitches on D0~7 ?
 
// Not sure about word access, is it LDS|UDS or LDS&UDS or nothing at all ?
assign LSPOE = ~RW | WORDACCESS | LSPCZONE;
assign LSPWE = RW | WORDACCESS | LSPCZONE;
assign CRDO = ~RW | WORDACCESS | CARDZONE;
assign CRDW = RW | WORDACCESS | CARDZONE;
assign CRDC = CRDO & CRDC;
 
// Inter-CPU comm.
// To do
 
// Inputs
// To do
 
// Wait states
// To do
 
</syntaxhighlight>
 
==NEO-D0==
 
Verified: NO.
 
<syntaxhighlight lang="verilog">
reg [1:0] CKDIV;
reg [2:0] SDIV;
reg 1MB;
reg [5:0] OUT;
reg [2:0] BNK;
 
assign XOUT = ~XIN;
assign 24M = XOUT;
assign 12M = CKDIV[0];
assign 6MB = ~CKDIV[1];
// Guessing the clock divider is a counter ?
always @(posedge 24M)
begin
  if (RESETP)
  begin
    1MB <= 1;
    SDIV <= 0;
    CKDIV <= 0;
  end
  else
  begin
    if (SDIV == 5)
    begin
      1MB <= ~1MB;
      SDIV <= 0;
    end
    else
      SDIV <= SDIV + 1;
    CKDIV <= CKDIV + 1;
  end
end
 
// Z80 address decode
// To do
 
assign {OUT6,OUT5,OUT4,OUT3,OUT2,OUT1} = RESETP ? OUT : 6'b000000;
assign {BNK2,BNK1,BNK0} = RESETP ? BNK : 3'b000;
 
always @(negedge BITWD0)
begin
  if (!A4)
    OUT <= D[5:0];
  else
    BNK <= D[2:0];
end
 
</syntaxhighlight>
 
==NEO-E0==
 
Verified: NO.
 
<syntaxhighlight lang="verilog">
assign AND0 = ANI0 & ANI1;
assign {A23I,A22I} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}};
 
// Memcard address stuff
// To do
</syntaxhighlight>
 
==NEO-F0==
 
Verified: NO.
 
<syntaxhighlight lang="verilog">
assign SLOT_NB = {SLOTC,SLOTB,SLOTA};
 
// Not sure about the behavior if SLOT_NB > 5
assign {SLOT5,SLOT4,SLOT3,SLOT2,SLOT1,SLOT0} =
  SYSTEMB ? 6'b111111 :
  (SLOT_NB == 3'b000) ? 6'b111110 :
  (SLOT_NB == 3'b001) ? 6'b111101 :
  (SLOT_NB == 3'b010) ? 6'b111011 :
  (SLOT_NB == 3'b011) ? 6'b110111 :
  (SLOT_NB == 3'b100) ? 6'b101111 :
  (SLOT_NB == 3'b101) ? 6'b011111 :
  8'b111111;
 
// Not sure about 6'b000000
assign D[7:0] = (DIPRD|~IN3) ? 8'bzzzzzzzz : A7 ? {IN01,IN00,6'b000000} : DIP[7:0];
 
// What is D5 ?
assign D[7:0] = (~DIPRD|IN3) ? 8'bzzzzzzzz : {CALDOUT,CALTP,1'b0,IN304,IN303,IN302,IN301,IN300};
 
</syntaxhighlight>
 
==NEO-G0==
 
Verified: NO.
 
<syntaxhighlight lang="verilog">
// What happens when both /CE are low ? Chip auto-destructs ?
 
// A0~7 <= B0~7 or C0~7 (B has priority)
assign {18,17,16,15,5,4,3,2} = 40 ? 39 ? 51 ? 8'bzzzzzzzz : {14,13,12,11,9,8,7,6} : {24,23,22,21,1,64,63,62} : 8'bzzzzzzzz;
// A8~15 <= B8~15 or C8~15 (B has priority)
assign {50,49,48,47,34,33,32,31} = 52 ? 39 ? 51 ? 8'bzzzzzzzz : {46,45,44,43,30,29,28,27} : {56,55,54,53,38,37,36,35} : 8'bzzzzzzzz;
 
// B0~7 <= A0~7
assign {24,23,22,21,1,64,63,62} = 39 ? 8'bzzzzzzzz : 40 ? 8'bzzzzzzzz : {18,17,16,15,5,4,3,2};
// B8~15 <= A8~15
assign {56,55,54,53,38,37,36,35} = 39 ? 8'bzzzzzzzz : 52 ? 8'bzzzzzzzz : {50,49,48,47,34,33,32,31};
 
// C0~7 <= A0~7
assign {14,13,12,11,9,8,7,6} = 51 ? 8'bzzzzzzzz : 40 ? 8'bzzzzzzzz : {18,17,16,15,5,4,3,2};
// C8~15 <= A8~15
assign {46,45,44,43,30,29,28,27} = 51 ? 8'bzzzzzzzz : 52 ? 8'bzzzzzzzz : {50,49,48,47,34,33,32,31};
 
assign 41 = 40 | 39;
assign 59 = 60 & 61;
</syntaxhighlight>
 
==NEO-I0==
 
Verified: NO.
 
<syntaxhighlight lang="verilog">
reg [15:0] S_LATCH;
 
assign {Q18,Q17,Q16,Q15,Q14,Q13,Q12,Q11,Q8,Q7,Q6,Q5,Q4,Q3,Q2,Q1} = S_LATCH;
 
always @(posedge PCK2B)
  S_LATCH <= {55,54,53,52,31,30,29,28,22,21,20,19,63,62,61,60};
 
assign SYNCOUT = SYNCIN ^ SYNCREV;
 
assign ORO0 = ORI0 | ORI1;
 
assign ROMOE = ROMOEL & ROMOEU;
 
// More to do...
</syntaxhighlight>
 
==NEO-ZMC==
 
See chip's page and MAME's source.
 
==NEO-ZMC2==
 
Need NEO-ZMC + Kyuu's code on chip's page :)


[[Category:Repairs]]
[[Category:Repairs]]
[[Category:Chips]]
[[Category:Chips]]

Latest revision as of 02:46, 16 January 2016

Dirty page for SNK chips replacements development.

Reading various [repair logs], it appears that dead or partially dead SNK chips are a common issue. It forces cannibalism and forcibly reduces the worldwide stock.

For preservation, it would be desirable to produce drop-in replacement chips to save original boards.

Considered solutions

Nobody likes rewiring to accomodate different pinouts, especially 80+ pins chips. Producing new ASICs is out of the question because of the price at low quantities, and because finding pin-compatible models todays would be difficult if not impossible.

The only solution would be adapter boards the size of the original chips, with castellated vias for surface mounting ? Furrtek (talk) 18:41, 15 January 2016 (CET)

  • Reconstruct the chip's logic with regular logic chips ? No: they're all too big. BGA parts aren't 5V compatible.
  • Use 2 boards on top of each other with a mezzanine connector ? No, no, no.
  • Use 1- or 2-gate SOT-23-5/6 chips ? Maybe in some cases, but would be expensive (long BOM, lots of parts to assemble).
  • Use a CPLD ? Probably the best solution. Altera's MAX3000 and Xilinx's XC9500 are 5V-tolerant and are still available at reasonable prices.

CPLD proposals

  • NEO-257: 53 I/Os, EPM3064 in TQFP100 ?
  • NEO-273: Only used in cartridges, rarely dies. A clone wouldn't be that useful ?
  • NEO-BUF: Really a pain, too small for QFP CPLDs. 74LVCH16245 in BGA56 ?
  • PRO-C0: Need pinout, quite big so EPM3128 in TQFP144 ?
  • NEO-C1: EPM3128 has enough I/Os, but too big in TQFP144.
  • NEO-D0: 55 I/Os, EPM3064 in TQFP100 ?
  • NEO-E0: 54 I/Os, EPM3064 in TQFP100 ?
  • NEO-F0: 60 I/Os, EPM3064 in TQFP100 ?
  • NEO-G0: 56 I/Os, EPM3064 in TQFP100 ?
  • NEO-I0: 56 I/Os, EPM3064 in TQFP100 ?
  • NEO-ZMC: Very small, can be found on AliExpress (January 2016). BGA ?
  • NEO-ZMC2: 71 I/Os, EPM3128 in TQFP100 ?
  • PCM: Only used in cartridges, rarely dies. 65 I/Os, EPM3064 in TQFP100 ?
  • NEO-DCR-T, NEO-SDR-T: Need pinouts, probably same problem as for NEO-C1.
  • LSPCs could be replaced but the I/O requirements directs to >$60 CPLDs.
  • Line buffers (PRO-B0, NEO-B1) could be replaced with MAX10's and level shifting ?. Might be too expensive.

Altera

MAX3000 I/Os.

  • EPM3032: 34. $1.61
  • EPM3064: 34 or 66. $2.93
  • EPM3128: 80 (or 96 but doesn't fit). $9.89

Xilinx

XC9500/XL I/Os.

  • XC9536: 34
  • XC9536XL: 36. $1.46
  • XC9572: 34, 69 or 72
  • XC9572XL: 34, 38, 52 or 72. $2.86
  • XC95108: 81. Hard to find.
  • XC95144/XL: 81. $7.25

Board proposals

Which board houses are castellation friendly ? Is classic 1.6mm good ?

QFP64R

QFP80R

QFP100R

Logic definitions

See https://github.com/neogeodev/SNKVerilog

Retrieved from "https://wiki.neogeodev.org/index.php?title=Replacement_chip&oldid=4606"