68k interrupts: Difference between revisions

From NeoGeo Development Wiki
Jump to navigation Jump to search
mNo edit summary
mNo edit summary
 
(2 intermediate revisions by the same user not shown)
Line 1: Line 1:
There are 3 interrupt levels on the AES and MVS, and 4 on the CD hardware.
The cartridge systems use 3 '''auto-vectored''' interrupt levels. The CD systems use 6 '''vectored''' interrupts, 3 of which are equivalent to the cartridge system's.


Interrupts need to be acknowledged by writing to register {{Reg|REG_IRQACK}}.
See [[68k vector table]].
*bit 2: Acknowledge vblank interrupt
 
Video-related interrupts must to be acknowledged to re-trigger in the future by writing to the register {{Reg|REG_IRQACK}}.
*bit 2: Acknowledge v-blank interrupt
*bit 1: Acknowledge [[timer interrupt]]
*bit 1: Acknowledge [[timer interrupt]]
*bit 0: Acknowledge cold start interrupt
*bit 0: Acknowledge reset interrupt (only occurs on cold boot ?)


Multiple bits can be set:
Multiple bits can be set:
Line 11: Line 13:
</syntaxhighlight>
</syntaxhighlight>


Bits 8~10 of the SR register can be used to mask them.
Bits 8~10 of the [[68k]]'s SR register is used to set the minimum priority:
 
<syntaxhighlight>
<syntaxhighlight>
move #$2000,SR    ; Enable all interrupts (+Supervisor mode)
move #$2000,SR    ; Accept all interrupts (+Supervisor mode)
move #$2700,SR    ; Disable all interrupts (+Supervisor mode)
move #$2700,SR    ; Ignore all interrupts (+Supervisor mode)
</syntaxhighlight>
</syntaxhighlight>
Note that the 68k's interrupt level setting is different from the interrupt configuration bits in {{Reg|REG_LSPCMODE}}.


=Vertical blank interrupt=
=Vertical blank interrupt=


The vblank interrupt is almost always used. It occurs when the rendering of a frame finishes (~60 times per second). See [[display timing]].
The v-blank interrupt is almost always used. It occurs when the rendering of a frame is about to start (~60 times per second). See [[display timing]].


=[[Timer interrupt]]=
=[[Timer interrupt]]=


The timer interrupt's behavior can be programmed through the [[GPU]]'s [[memory mapped registers]]. It is triggered by a 32-bit down counter clocked by the 6MHz pixel clock, and a corresponding reset register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7ns ('''dangerous interrupt flood''') to 11.9 minutes (?).
The timer interrupt's behavior can be programmed through the [[LSPC]]'s [[memory mapped registers]]. It is triggered by a 32-bit down counter clocked by the 6MHz pixel clock, and a corresponding reset register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7ns ('''would cause an interrupt flood !''') to a little over 11.9 minutes.


It can be used for special video effects such as [[scanline effects]], for example:
It can be used for special video effects such as [[scanline effects]], for example:
Line 35: Line 38:
=AES/MVS interrupt levels=
=AES/MVS interrupt levels=


*Vblank: Level 0
*Level 1: V-blank
*Timer: Level 1
*Level 2: Timer
*Pending after cold reset: Level 2
*Level 3: Pending after reset


=CD interrupt levels=
=CD interrupt levels=


*VBlank: Level 1 !
The V-blank and Timer levels '''are swapped''' compared to the cartridge systems.
*Timer: Level 0 !
*CDC interrupt: Level 3 !


Level 2 isn't used ?
*Level 1: Timer
*Level 2: V-blank
*Level 3: Not used ?
*Vector 21: CD host decoder interrupt (data ready)
*Vector 22: CD drive communication start
*Vector 23: Used but not understood


[[Category:Base system]]
[[Category:Base system]]
[[Category:Code]]
[[Category:Code]]

Latest revision as of 23:50, 16 October 2023

The cartridge systems use 3 auto-vectored interrupt levels. The CD systems use 6 vectored interrupts, 3 of which are equivalent to the cartridge system's.

See 68k vector table.

Video-related interrupts must to be acknowledged to re-trigger in the future by writing to the register REG_IRQACK.

  • bit 2: Acknowledge v-blank interrupt
  • bit 1: Acknowledge timer interrupt
  • bit 0: Acknowledge reset interrupt (only occurs on cold boot ?)

Multiple bits can be set: 

move	#$0007,REG_IRQACK     ; Acknowledge all interrupts

Bits 8~10 of the 68k's SR register is used to set the minimum priority: 

move	#$2000,SR     ; Accept all interrupts (+Supervisor mode)
move	#$2700,SR     ; Ignore all interrupts (+Supervisor mode)

Note that the 68k's interrupt level setting is different from the interrupt configuration bits in REG_LSPCMODE.

Vertical blank interrupt

The v-blank interrupt is almost always used. It occurs when the rendering of a frame is about to start (~60 times per second). See display timing.

Timer interrupt

The timer interrupt's behavior can be programmed through the LSPC's memory mapped registers. It is triggered by a 32-bit down counter clocked by the 6MHz pixel clock, and a corresponding reset register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7ns (would cause an interrupt flood !) to a little over 11.9 minutes.

It can be used for special video effects such as scanline effects, for example:

AES/MVS interrupt levels

  • Level 1: V-blank
  • Level 2: Timer
  • Level 3: Pending after reset

CD interrupt levels

The V-blank and Timer levels are swapped compared to the cartridge systems.

  • Level 1: Timer
  • Level 2: V-blank
  • Level 3: Not used ?
  • Vector 21: CD host decoder interrupt (data ready)
  • Vector 22: CD drive communication start
  • Vector 23: Used but not understood
Retrieved from "https://wiki.neogeodev.org/index.php?title=68k_interrupts&oldid=8325"