Revision as of 01:28, 12 October 2016


Package	QFP64R
Manufacturer
First use	1990 ?
Used on	MV2B ...

MVS specific chip that does a bunch of unrelated things.

S ROM 16bit address latch for SFIX, same as S ROM portion of NEO-273
SM1 /CS output when Z80 is reading from ROM and onboard ROMs are enabled
ROMOE output for cartridge(s) PROG board
Video sync inversion (or not) to JAMMA connector
Coin counter and coin lockout outputs

Pinout

File:Neo-i0 pinout.png

OpenOffice Draw file: File:Neo-i0.odg

A0~A3,A7: 68k address bus
P0~P15: GPU multiplexed bus
Q01~Q18: SFIX ROM address lines
SM1CS(ORO0): SM1 ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1)
SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?)
Q21, Q22: METER1, METER2
Q23, Q24: LOCK1, LOCK2
DS0, DS1: Data select for 2-slot systems made from SLOT0, SLOT1, PORTADRS and ROMOE, goes to a NEO-G0
CUNTOUT: Address decode from NEO-F0

@@ Line 1: / Line 1: @@
-[[File:neo-i0.jpg|right|thumb|NEO-I0 chip found on a [[MV2B]] MVS board.]]
+{{ChipInfo
+|picture=neo-i0.jpg
+|pkg=QFP64R
+|manu=fujitsu
+|date=1990 ?
+|gates=
+|used_on={{PCB|MV2B}} ...
+}}
 MVS specific chip that does a bunch of unrelated things.
-*[[S ROM]] 16bit address latch for [[SFIX]], same as S ROM portion of [[NEO-273]]
+* [[S ROM]] 16bit address latch for [[SFIX]], same as S ROM portion of {{Chipname|NEO-273}}
-*[[SM1]] /CS output when Z80 is reading from ROM and onboard ROMs are enabled
+* [[SM1]] /CS output when {{Chipname|Z80}} is reading from ROM and onboard ROMs are enabled
-*/ROMOE output for cartridge(s) [[PROG board]]
+* {{Sig|ROMOE|ROMOE}} output for cartridge(s) [[PROG board]]
-*Video sync inversion (or not) to JAMMA edge
+* Video sync inversion (or not) to [[JAMMA_connector_pinout|JAMMA connector]]
-*Coin counter and coin lockout output
+* [[Coin counter]] and [[coin lockout]] outputs
-Why is A3 needed ?
 =Pinout=
@@ Line 19: / Line 24: @@
 |
-*A0~A3,A7: [[68k]] address bus
+*A0~A3,A7: {{Chipname|68k}} address bus
 *P0~P15: [[GPU]] multiplexed bus
 *Q01~Q18: [[SFIX]] ROM address lines
@@ Line 26: / Line 31: @@
 *Q21, Q22: METER1, METER2
 *Q23, Q24: LOCK1, LOCK2
-*DS0, DS1: Data select for 2-slot systems made from SLOT0, SLOT1, PORTADRS and ROMOE, goes to a [[NEO-G0]]
+*DS0, DS1: Data select for 2-slot systems made from SLOT0, SLOT1, PORTADRS and ROMOE, goes to a {{Chipname|NEO-G0}}
-*CUNTOUT: Address decode from [[NEO-F0]]
+*CUNTOUT: Address decode from {{Chipname|NEO-F0}}
 |}
 [[Category:Chips]]

NEO-I0: Difference between revisions

Revision as of 01:28, 12 October 2016

Pinout

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