LSPC2-A2: Difference between revisions

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[[File:aes_lspc2a2.jpg|right|thumb|LSPC2-A2 graphics chip found in an AES system.]]
{{ChipInfo
|picture=aes_lspc2a2.jpg
|pkg=QFP176
|manu=fujitsu
|date=1992 ?
|gates=
|used_on={{PCB|NEO-AES3-4 board}} {{PCB|MV1FZS}}...
}}


The LSPC chips are only found in cartridge systems, they provide pixel data for the [[Video DAC]]. (the line buffer for color data is most likely in the NEO-B1 but don't know for sure...).
LSPC2-A2 is the second generation Line SPrite Controller, it is only found in cartridge systems.


LSPC-A0 chips can be found on early MVS slots and AES systems and work alongside the [[PRO-B0]] chip.  LSPC2-A2 chips are found in second revision systems and work with the [[NEO-B1]] chip.
*Generates {{Chipname|S ROM}}, {{Chipname|C ROM}} and {{Chipname|LO}} ROM addresses based on current display line and [[VRAM]] content
*Sync output
*{{Chipname|NEO-B1}} control
*68k IRQs
*68k VRAM access arbitration


==Graphics==
First generation {{Chipname|LSPC-A0}} chips can be found in earlier systems.


Two separate buses run in parallel to fetch data from [[VRAM]] for rendering the screen.  Each bus connects to a pair of 8bit chips, forming a 16bit bus.
=Graphics=


*VRAM 0000-7FFF - 2x 62256/43256 (120ns(?) or faster)
Two separate busses run in parallel to fetch data from the two VRAM zones. Each bus connects to a pair of 8-bit RAM chips.
*VRAM 8000-87FF - 2x 5814/5863/6116 (45ns or faster)


The LSPC arbitrates all VRAM access and allows for 68k access at any time during rendering without display glitches.  The interface is slow and data writes are ignored when games write VRAM too quickly, especially with overclocked systems *specifics go here maybe*.
*VRAM $0000~$7FFF - 2x 62256/43256
*VRAM $8000~$87FF - 2x 5814/5863/6116


It shares a 24bit bus with the [[NEO-B1]] which goes out to the [[Pinouts#Cartridges|CHA connector]] on the cart slot for addressing [[S ROM]]s, [[C ROM]]s and the on-board [[LO]] ROM.
The LSPC arbitrates all VRAM access and allows for {{Chipname|68k}} access at any time during rendering without display glitches if they aren't made too fast. See [[VRAM]] for timing requirements.


==IRQ==
It shares the 24-bit [[P bus]] (P0~P23) with NEO-B1 and the on-board [[L0 ROM]], which goes out to the [[Pinouts#Cartridges|CHA connector]] on the cart slot for addressing {{Chipname|S ROM}}s and {{Chipname|C ROM}}s.


All 3 [[68k interrupts]] are generated by this chip.
=IRQs=


==Pinout==
All 3 possible [[68k interrupts]] are generated by this chip.


(Max size:[[:File:lspc2-a2_pinout.png]])<br>
=Pinout=
[[File:lspc2-a2_pinout.png|640px]]


Need to find: 28,87,128,133
{{Pinout|LSPC2-A2|640}}


*A1~A3: [[68k]] address bus
*A1~A3: 68k address bus
*D0~D15: [[68k]] data bus
*D0~D15: 68k data bus
*B0~B14: VRAM bank 0 address bus
*/LSPOE, /LSPWE: Decoded chip read/write
*E0~E15: VRAM bank 0 data bus
*B0~B14: Low VRAM address bus
*C0~C10: VRAM bank 1 address bus
*E0~E15: Low VRAM data bus
*F0~F15: VRAM bank 1 data bus
*/BOE, /BWE: Low VRAM read/write
*P0~P13: "Internal" multiplexed bus
*C0~C10: Fast VRAM address bus
*/BOE,/BWE: VRAM bank 0 read/write
*/CWE: Fast VRAM write enable
*/CWE: VRAM bank 1 write enable
*F0~F15: Fast VRAM data bus
*/LSPOE,/LSPWE: Chip read/write (VRAM access,...)
*P0~P23: Multiplexed [[P bus]]
*/RES: Reset
*1H1: [[Clock]] used by NEO-B1
*1H1/2H1:
*2H1: S ROM A3
*24M: 24MHz clock ?
*24M: 24MHz clock input from {{Chipname|NEO-D0}}
*4M: 4MHz clock ?
*8M: 8MHz clock output to the {{Chipname|YM2610}}
*CC4:
*4M: 4MHz clock output to the {{Chipname|Z80}}
*DIVI/DIVO: Frequency divider ?
*CA4: C ROM A4
*DOTA/DOTB: See [[NEO-ZMC2]]
*DIVI, DIVO, REF, TSTD: Independant frequency division circuit used by the [[video PLL]]
*EVEN1/EVEN2:
*EVEN1, EVEN2, H, LOAD: C ROM serializer control, see {{Chipname|NEO-ZMC2}}
*H:
*DOTA, DOTB: Pixel opacity inputs from NEO-ZMC2
*INT:
*IP0, IP1: 68k interrupt lines
*IP0/IP1:
*PK1: Clock to latch C ROM address from P bus
*LOAD:
*PK2: Clock to latch S ROM address from P bus
*PK1/PK2:
*RESETP: Reset pulse output
*REF:
*SYNC: Video sync signal output
*RESETF:
*TST: Enable test mode, uses D0~D10 (always tied to ground)
*SCH?:
*VCS: L0 ROM output enable
*SL1?/SL2?:
*WE1~WE4: Synchronous write enable signals for NEO-B1
*SW?:148?
*CK1~CK4: Clocks for rendering and output for NEO-B1
*SYNC:
*SS1, SS2: NEO-B1 control
*TST:
*BNKB: Video blanking (for V-blank)
*TST0:
*CHBL: Video blanking (for H-blank, sent to NEO-B1)
*VCS:
*PAL/NTSC: Video mode selection, latched during reset
*WE1~WE4,CK1~CK4,SS1,SS2: [[NEO-B1]] communication
 
*?NK2:
*CM?L:


[[Category:Chips]]
[[Category:Chips]]

Latest revision as of 01:10, 8 July 2018

Package QFP176
Manufacturer
First use 1992 ?
Used on NEO-AES3-4 board MV1FZS...

LSPC2-A2 is the second generation Line SPrite Controller, it is only found in cartridge systems.

  • Generates S ROM, C ROM and LO ROM addresses based on current display line and VRAM content
  • Sync output
  • NEO-B1 control
  • 68k IRQs
  • 68k VRAM access arbitration

First generation LSPC-A0 chips can be found in earlier systems.

Graphics

Two separate busses run in parallel to fetch data from the two VRAM zones. Each bus connects to a pair of 8-bit RAM chips.

  • VRAM $0000~$7FFF - 2x 62256/43256
  • VRAM $8000~$87FF - 2x 5814/5863/6116

The LSPC arbitrates all VRAM access and allows for 68k access at any time during rendering without display glitches if they aren't made too fast. See VRAM for timing requirements.

It shares the 24-bit P bus (P0~P23) with NEO-B1 and the on-board L0 ROM, which goes out to the CHA connector on the cart slot for addressing S ROMs and C ROMs.

IRQs

All 3 possible 68k interrupts are generated by this chip.

Pinout


Edit this pinout

  • A1~A3: 68k address bus
  • D0~D15: 68k data bus
  • /LSPOE, /LSPWE: Decoded chip read/write
  • B0~B14: Low VRAM address bus
  • E0~E15: Low VRAM data bus
  • /BOE, /BWE: Low VRAM read/write
  • C0~C10: Fast VRAM address bus
  • /CWE: Fast VRAM write enable
  • F0~F15: Fast VRAM data bus
  • P0~P23: Multiplexed P bus
  • 1H1: Clock used by NEO-B1
  • 2H1: S ROM A3
  • 24M: 24MHz clock input from NEO-D0
  • 8M: 8MHz clock output to the YM2610
  • 4M: 4MHz clock output to the Z80
  • CA4: C ROM A4
  • DIVI, DIVO, REF, TSTD: Independant frequency division circuit used by the video PLL
  • EVEN1, EVEN2, H, LOAD: C ROM serializer control, see NEO-ZMC2
  • DOTA, DOTB: Pixel opacity inputs from NEO-ZMC2
  • IP0, IP1: 68k interrupt lines
  • PK1: Clock to latch C ROM address from P bus
  • PK2: Clock to latch S ROM address from P bus
  • RESETP: Reset pulse output
  • SYNC: Video sync signal output
  • TST: Enable test mode, uses D0~D10 (always tied to ground)
  • VCS: L0 ROM output enable
  • WE1~WE4: Synchronous write enable signals for NEO-B1
  • CK1~CK4: Clocks for rendering and output for NEO-B1
  • SS1, SS2: NEO-B1 control
  • BNKB: Video blanking (for V-blank)
  • CHBL: Video blanking (for H-blank, sent to NEO-B1)
  • PAL/NTSC: Video mode selection, latched during reset
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