LSPC2-A2: Difference between revisions
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*VRAM $8000~$87FF - 2x 5814/5863/6116 (45ns or faster) | *VRAM $8000~$87FF - 2x 5814/5863/6116 (45ns or faster) | ||
The LSPC arbitrates all VRAM access and allows for {{Chipname|68k}} access at (almost) any time during rendering without display glitches. The interface is slow and some access can be ignored when too fast, especially with [[ | The LSPC arbitrates all VRAM access and allows for {{Chipname|68k}} access at (almost) any time during rendering without display glitches. The interface is slow and some access can be ignored when too fast, especially with [[overclocking|overclocked]] systems. | ||
It shares a 24-bit [[P bus]] (P0~P23) with NEO-B1 and the on-board L0 ROM, which goes out to the [[Pinouts#Cartridges|CHA connector]] on the cart slot for addressing {{Chipname|S ROM}}s and {{Chipname|C ROM}}s. | It shares a 24-bit [[P bus]] (P0~P23) with NEO-B1 and the on-board L0 ROM, which goes out to the [[Pinouts#Cartridges|CHA connector]] on the cart slot for addressing {{Chipname|S ROM}}s and {{Chipname|C ROM}}s. | ||
Revision as of 11:26, 29 December 2016
| |
| Package | QFP176 |
| Manufacturer | 
|
| First use | 1992 ? |
| Used on | NEO-AES3-4 MV1F
MV1FZ... |
LSPC2-A2 is the second generation Line SPrite Controller, it is only found in cartridge systems.
- Generates S ROM, C ROM and LO ROM addresses based on current display line and VRAM content
- Sync output
- NEO-B1 control
- 68k IRQs
- 68k VRAM access arbitration
LSPC-A0 chips can be found on early MVS slots and AES systems and work alongside the PRO-B0 chip.
Graphics
Two separate busses run in parallel to fetch data from the two VRAM zones. Each bus connects to a pair of 8-bit RAM chips.
- VRAM $0000~$7FFF - 2x 62256/43256 (120ns(?) or faster)
- VRAM $8000~$87FF - 2x 5814/5863/6116 (45ns or faster)
The LSPC arbitrates all VRAM access and allows for 68k access at (almost) any time during rendering without display glitches. The interface is slow and some access can be ignored when too fast, especially with overclocked systems.
It shares a 24-bit P bus (P0~P23) with NEO-B1 and the on-board L0 ROM, which goes out to the CHA connector on the cart slot for addressing S ROMs and C ROMs.
IRQs
All 3 (2 ?) 68k interrupts are generated by this chip.
Pinout
(Max size:File:lspc2-a2_pinout.png)
File:Lspc2-a2 pinout.png
OpenOffice Draw file: File:Lspc2-a2.odg
Need to find: 28,87,128,133
- A1~A3: 68k address bus
- D0~D15: 68k data bus
- B0~B14: VRAM bank 0 address bus
- E0~E15: VRAM bank 0 data bus
- C0~C10: VRAM bank 1 address bus
- F0~F15: VRAM bank 1 data bus
- P0~P23: "Internal" multiplexed P bus
- /BOE,/BWE: VRAM bank 0 read/write
- /CWE: VRAM bank 1 write enable
- /LSPOE,/LSPWE: Chip read/write, provided by NEO-C1
- /RES: Reset
- 1H1:
- 2H1: S ROM A3
- 24M: 24MHz clock input from NEO-D0
- 4M: 4MHz clock output to Z80
- CA4: C ROM A4
- DIVI/DIVO: Frequency divider ?
- EVEN1, EVEN2, H, LOAD: C ROM multiplexer control, see NEO-ZMC2
- DOTA/DOTB: Transparency input from NEO-ZMC2
- INT:
- IP0/IP1: 68k interrupt level
- PK1: Clock to latch C ROM address from P bus
- PK2: Clock to latch S ROM address from P bus
- REF:
- RESETF:
- SCH?:
- SL1?/SL2?:
- 6M: 6MHz clock output to YM2610 and cartridge connector
- 6MB: Pixel clock
- SYNC: Video sync signal
- TST:
- TST0:
- VCS:
- WE1~WE4: Synchronous write enable signals for NEO-B1
- CK1~CK4: Clocks for rendering in, and output from NEO-B1
- SS1, SS2: NEO-B1 control, can't remember what they do. Line buffer switch ?
- BNKB: Video blanking (for V-blank)
- CHBL: Video blanking (for H-blank, sent to NEO-B1)