
Package	QFP100R
Manufacturer
First use	1992 ?
Used on	NEO-AES3-4 board...

The NEO-C1 is a multi-purpose keystone chip used for address decoding, inter-CPU communications, wait cycle generation, and player inputs on systems based on the 2nd generation chipset.

It maps itself to 68k even byte accesses.

Pinout

Edit this pinout

Internal schematics

https://github.com/furrtek/SiliconRE/tree/master/SNK/NEO-C1

Signals

Inputs

REG_P1CNT:

IN00: Up P1
IN01: Down P1
IN02: Left P1
IN03: Right P1
IN04: A P1
IN05: B P1
IN06: C P1
IN07: D P1

REG_P2CNT:

IN10: Up P2
IN11: Down P2
IN12: Left P2
IN13: Right P2
IN14: A P2
IN15: B P2
IN16: C P2
IN17: D P2

REG_STATUS_B:

IN20: Start P1
IN21: Select P1
IN22: Start P2
IN23: Select P2
IN24: Memory card inserted
IN25: Memory card inserted
IN26: Memory card write protect
IN27: System type (home/arcade)

68k

A17~A21: 68k address bus
A22I~A23I: NEO-E0 address input
D8~D15: 68k data bus
R/W, UDS, LDS, AS, DTACK: 68k bus control signals
68KCLK: 12MHz 68k clock
ROMWAIT, PWAIT0, PWAIT1, PDTACK: signals from cart PROG board to configure wait cycles.

Decoded signals

The following output and write enables have an upper(U)/lower(L) byte enable signal based on /UDS and /LDS from the 68k.

ROMOEU, ROMOEL: $000000-$0FFFFF read, 68k program ROM on cart / vector table
WRU, WRL, WWU, WWL: $100000-$1FFFFF read/write 68k user RAM
PORTOEU, PORTOEL, PORTWEU, PORTWEL: $200000-$2FFFFF read/write, 68k program ROM and/or security chips on cart
SROMOEU, SROMOEL: $C00000-$CFFFFF read system ROM
SRAMOEU, SRAMOEL, SRAMWEU, SRAMWEL: $D00000-$DFFFFF read/write battery-backed RAM

When A23I A22I A21 A20 = 1100 and RW = 1, either SROMOEU and SROMOEL should be low depending on UDS and LDS.

The following are expected to be word accessed, byte writes and reads are ignored or do not work as expected.

CRDO, CRDW: $800000-$BFFFFF read/write memory card
CRDC: Memory card select
LSPOE, LSPWE: $3C0000-$3DFFFF read/write LSPC2-A2
PAL: $400000-$7FFFFF read/write palette RAM

Z80 I/O

SDD0~SDD7: Z80 data bus used for 68k/Z80 communication
SDZ80R, SDZ80W: read / write signals for Z80 communication
SDW: signals that 68k has written a byte to Z80 port, will make NEO-D0 generate an interrupt if enabled
SDZ80CLR: reset stored byte

CONNECTIONS (French)

SCHEM	PIN	M68000	NEO-E0	NEO-B1	REAR SLOT	FRONT SLOT	WRAM1	WRAM2	NEO-G0	74HC04	CRE401/5	CRE401/4	CRE401/3	CRE401/2	CRE401/1	LSPC-A2	NEO-DO	Z80	HM6116	YM2610	74HC259	NEO-PO	CARD IC	74HC32
DIPRD0	1
DIPRD1	2
VCC	3
NC	4
ROMOEU	5		21A		60
WRU	6				22
WWU	7				27
LSPOE	8								172
LSPWE	9								173
PORTOEU	10		28A
PORTWEU	11		30A
SROMOEU	12			60
SRAMOEU	13
SRAMWEU	14
GND	15
PAL	16			39
VPA	17	21
PADRS	18		48A
DTACK	19	10
A17	20	45	36	112	19B
A18	21	46	37	113	20B
A19	22	47	38	114	21B
A20	23	48	48	115
A21	24	50	49	116
A22I	25		55	117
A23I	26		54	118
CRDC	27				13									7 & 42
VCC	28
SDW	29				33
CRDO	30															9
CRDW	31														5
RW	32	9		91	19A		40/52
UDS	33	7			89
LDS	34	8			89
AS	35	6			88
68KCLC	36	15					22
ROMWAIT	37		28B
PWAIT0	38		30B
PWAIT1	39		31B
GND	40
PDTACK	41		29B
IN00	42				3
IN01	43				5
IN02	44				7
IN03	45				9
…	…	…	…	…	…	…	…	…	…	…	…	…	…	…

NEO-C1

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