68k interrupts: Difference between revisions

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There are 3 interrupt levels on the AES and MVS. Only 2 on the CD hardware.
The cartridge systems use 3 '''auto-vectored''' interrupt levels. The CD systems use 6 '''vectored''' interrupts, 3 of which are equivalent to the cartridge system's.


Interrupts need to be acknowledged by writing to register $3C000C (REG_IRQACK).
See [[68k vector table]].
*bit2: Ack VBlank interrupt
*bit1: Ack Timer interrupt
*bit0: Ack level 3


<pre>
Video-related interrupts must to be acknowledged to re-trigger in the future by writing to the register {{Reg|REG_IRQACK}}.
*bit 2: Acknowledge v-blank interrupt
*bit 1: Acknowledge [[timer interrupt]]
*bit 0: Acknowledge reset interrupt (only occurs on cold boot ?)
 
Multiple bits can be set:
<syntaxhighlight>
move #$0007,REG_IRQACK    ; Acknowledge all interrupts
move #$0007,REG_IRQACK    ; Acknowledge all interrupts
</pre>
</syntaxhighlight>
 
Bits 8~10 of the [[68k]]'s SR register is used to set the minimum priority:
<syntaxhighlight>
move #$2000,SR    ; Accept all interrupts (+Supervisor mode)
move #$2700,SR    ; Ignore all interrupts (+Supervisor mode)
</syntaxhighlight>
 
Note that the 68k's interrupt level setting is different from the interrupt configuration bits in {{Reg|REG_LSPCMODE}}.


Bits 8~10 of the SR register are used to mask them.
=Vertical blank interrupt=


<pre>
The v-blank interrupt is almost always used. It occurs when the rendering of a frame is about to start (~60 times per second). See [[display timing]].
move #$2000,SR    ; Enable all interrupts (+Supervisor mode)
move #$2700,SR    ; Disable all interrupts (+Supervisor mode)
</pre>


== Vertical Blank interrupt ==
=[[Timer interrupt]]=


The VBlank interrupt is almost always used. It occurs everytime a new frame is traced (~60Hz). See [[display timing]].
The timer interrupt's behavior can be programmed through the [[LSPC]]'s [[memory mapped registers]]. It is triggered by a 32-bit down counter clocked by the 6MHz pixel clock, and a corresponding reset register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7ns ('''would cause an interrupt flood !''') to a little over 11.9 minutes.


== [[Timer interrupt]] ==
It can be used for special video effects such as [[scanline effects]], for example:
* The interlaced Sammy logo in [[Viewpoint]]
* [[Sengoku 2]]'s intro
* The road in [[Riding hero]]
* [[Neo Turf Masters]]'s ground perspective
* ...


The Timer interrupt's behavior can be programmed through the [[GPU]]'s [[memory mapped registers]]. It is made of a down-counting 32bit register clocked by the 6MHz pixel clock, and a corresponding set register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7µs to 11.9 minutes (?). The Sammy logo at the start of [[Viewpoint]] is an example of its use. [[Sengoku 3]] and [[Neo Turf Masters]] are also known to rely on them to do [[scanline effects]].
=AES/MVS interrupt levels=


== AES/MVS interrupts levels ==
*Level 1: V-blank
*Level 2: Timer
*Level 3: Pending after reset


*VBlank: Level 0
=CD interrupt levels=
*Timer: Level 1
*Pending at startup ?: Level 2


== CD interrupts levels ==
The V-blank and Timer levels '''are swapped''' compared to the cartridge systems.


*VBlank: Level 1
*Level 1: Timer
*Timer: Level 0
*Level 2: V-blank
*Level 3: Not used ?
*Vector 21: CD host decoder interrupt (data ready)
*Vector 22: CD drive communication start
*Vector 23: Used but not understood


[[Category:Base system]]
[[Category:Base system]]
[[Category:Code]]
[[Category:Code]]

Latest revision as of 23:50, 16 October 2023

The cartridge systems use 3 auto-vectored interrupt levels. The CD systems use 6 vectored interrupts, 3 of which are equivalent to the cartridge system's.

See 68k vector table.

Video-related interrupts must to be acknowledged to re-trigger in the future by writing to the register REG_IRQACK.

  • bit 2: Acknowledge v-blank interrupt
  • bit 1: Acknowledge timer interrupt
  • bit 0: Acknowledge reset interrupt (only occurs on cold boot ?)

Multiple bits can be set:

move	#$0007,REG_IRQACK     ; Acknowledge all interrupts

Bits 8~10 of the 68k's SR register is used to set the minimum priority:

move	#$2000,SR     ; Accept all interrupts (+Supervisor mode)
move	#$2700,SR     ; Ignore all interrupts (+Supervisor mode)

Note that the 68k's interrupt level setting is different from the interrupt configuration bits in REG_LSPCMODE.

Vertical blank interrupt

The v-blank interrupt is almost always used. It occurs when the rendering of a frame is about to start (~60 times per second). See display timing.

Timer interrupt

The timer interrupt's behavior can be programmed through the LSPC's memory mapped registers. It is triggered by a 32-bit down counter clocked by the 6MHz pixel clock, and a corresponding reset register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7ns (would cause an interrupt flood !) to a little over 11.9 minutes.

It can be used for special video effects such as scanline effects, for example:

AES/MVS interrupt levels

  • Level 1: V-blank
  • Level 2: Timer
  • Level 3: Pending after reset

CD interrupt levels

The V-blank and Timer levels are swapped compared to the cartridge systems.

  • Level 1: Timer
  • Level 2: V-blank
  • Level 3: Not used ?
  • Vector 21: CD host decoder interrupt (data ready)
  • Vector 22: CD drive communication start
  • Vector 23: Used but not understood