NEO-I0: Difference between revisions
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*A0~A3,A7: {{Chipname|68k}} address bus | *A0~A3,A7: {{Chipname|68k}} address bus | ||
*P0~P15: [[GPU]] multiplexed bus | *P0~P15: [[GPU]] multiplexed bus | ||
*Q01~Q18: | *Q01~Q18: SFIX ROM address lines | ||
*SM1CS(ORO0): [[SM1]] ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1) | *SM1CS(ORO0): [[SM1]] ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1) | ||
*SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?) | *SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?) | ||
Revision as of 10:07, 19 February 2017
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| Package | QFP64R |
| Manufacturer | 
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| First use | 1990 ? |
| Used on | MV2B ... |
MVS specific chip that does a bunch of unrelated things.
- S ROM 16bit address latch for the SFIX ROM, same as S ROM portion of NEO-273
- SM1 /CS output when Z80 is reading from ROM and onboard ROMs are enabled
- ROMOE output for cartridge(s) PROG board
- Video sync inversion (or not) to JAMMA connector
- Coin counter and coin lockout outputs
Pinout
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OpenOffice Draw file: File:Neo-i0.odg |
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