Memory mapped registers: Difference between revisions

From NeoGeo Development Wiki
Jump to navigation Jump to search
mNo edit summary
No edit summary
Line 1: Line 1:
=Register descriptions=
==I/O registers==
==I/O registers==
Odd/even infos and mirroring ranges aren't tested !


{| class="regdef"
{| class="regdef"
|'''Address'''
|'''Address'''
|'''Decode mask'''
|'''Name'''
|'''Name'''
|'''Read'''
|'''Read'''
Line 10: Line 11:
|'''Handled by'''
|'''Handled by'''
|-
|-
|$300000~$31FFFE, even bytes
|$300000
|$FE0001
|REG_P1CNT
|REG_P1CNT
|Player 1 controls or [[trackball]] data (active low)
|Player 1 controls or [[trackball]] data (active low)
Line 17: Line 19:
|[[NEO-C1]]
|[[NEO-C1]]
|-
|-
|$300001~?, odd bytes
|$300001
|$FE0081
|REG_DIPSW
|REG_DIPSW
|[[Hardware DIPs]] (active low)
|[[Hardware DIPs]] (active low)
Line 24: Line 27:
|[[NEO-F0]] (read), [[NEO-B1]] (write)
|[[NEO-F0]] (read), [[NEO-B1]] (write)
|-
|-
|$300081~?, odd bytes
|$300081
|?
|$FE0081
|REG_SYSTYPE
|IN01 to D7 (test switch) and TYPE to D6, see [[NEO-F0]]
|IN01 to D7 (test switch) and TYPE to D6, see [[NEO-F0]]
|?
|?
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
|$320000~$33FFFE, even bytes
|$320000
|$FE0001
|REG_SOUND
|REG_SOUND
|[[68k/Z80 communication|Read Z80 reply code]]
|[[68k/Z80 communication|Read Z80 reply code]]
Line 36: Line 41:
|[[NEO-C1]]
|[[NEO-C1]]
|-
|-
|$320001~?, odd bytes
|$320001
|$FE0001
|REG_STATUS_A  
|REG_STATUS_A  
|Switch inputs are active low
|Switch inputs are active low
Line 43: Line 49:
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
|$340000~$37FFFE, even bytes
|$340000
|$FE0001
|REG_P2CNT
|REG_P2CNT
|Player 2 controls (active low)
|Player 2 controls (active low)
Line 50: Line 57:
|[[NEO-C1]]
|[[NEO-C1]]
|-
|-
|$380000~$3BFFFE(?), even bytes
|$380000
|$FE0001
|REG_STATUS_B
|REG_STATUS_B
|Aux inputs (active low)
|Aux inputs (active low)
Line 57: Line 65:
|[[NEO-C1]]
|[[NEO-C1]]
|-
|-
|$380001~?, odd bytes
|$380001
|$FE0071
|REG_POUTPUT
|REG_POUTPUT
|?
|?
Line 64: Line 73:
|[[NEO-D0]]
|[[NEO-D0]]
|-
|-
|$380011~?, odd bytes
|$380011
|$FE0071
|REG_CRDBANK
|REG_CRDBANK
|?
|?
Line 70: Line 80:
|[[NEO-D0]]
|[[NEO-D0]]
|-
|-
|$380021~?, odd bytes
|$380021
|$FE00F1
|REG_SLOT
|REG_SLOT
|?
|?
Line 77: Line 88:
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
|$380031~?, odd bytes
|$380031
|$FE00F1
|REG_LEDLATCHES
|REG_LEDLATCHES
|?
|?
Line 84: Line 96:
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
|$380041~?, odd bytes
|$380041
|$FE00F1
|REG_LEDDATA
|REG_LEDDATA
|?
|?
Line 90: Line 103:
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
|$380051~?, odd bytes
|$380051
|$FE00F1
|REG_RTCCTRL
|REG_RTCCTRL
|?
|?
Line 96: Line 110:
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
|$380061~?, odd bytes
|$380061
|$FE0071
|REG_RESETCC1
|REG_RESETCC1
|
|?
|Any, [[coin counter]] 1 floats
|Any, [[coin counter]] 1 floats
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$380063~?, odd bytes
|$380063
|$FE0071
|REG_RESETCC2
|REG_RESETCC2
|
|?
|Any, coin counter 2 floats
|Any, coin counter 2 floats
||[[NEO-I0]]
||[[NEO-I0]]
|-
|-
|$380065~?, odd bytes
|$380065
|$FE0071
|REG_RESETCL1
|REG_RESETCL1
|
|?
|Any, [[coin lockout]] 1 floats
|Any, [[coin lockout]] 1 floats
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$380067~?, odd bytes
|$380067
|$FE0071
|REG_RESETCL2
|REG_RESETCL2
|
|?
|Any, coin lockout 2 floats
|Any, coin lockout 2 floats
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$3800D1~?, odd bytes
|$3800D1
|$FE0071
|?
|?
|
|REG_RTCOUT
|Write to RTC
|Write to RTC
uPD4990AWrite(byteValue & 2, byteValue & 4, byteValue & 1);
uPD4990AWrite(byteValue & 2, byteValue & 4, byteValue & 1);
|?
|[[NEO-F0]]
|-
|-
|$3800E1~?, odd bytes
|$3800E1
|$FE0071
|REG_SETCC1
|REG_SETCC1
|?
|?
Line 133: Line 153:
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$3800E3~?, odd bytes
|$3800E3
|$FE0071
|REG_SETCC2
|REG_SETCC2
|?
|?
Line 139: Line 160:
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$3800E5~?, odd bytes
|$3800E5
|$FE0071
|REG_SETCL1
|REG_SETCL1
|?
|?
Line 145: Line 167:
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$3800E7~?, odd bytes
|$3800E7
|$FE0071
|REG_SETCL2
|REG_SETCL2
|?
|?
Line 153: Line 176:


==System registers==
==System registers==
Handled by a 74HC259 adressable latch on cart systems. Byte writes only.
Handled by a 74HC259 adressable latch on cart systems. Byte writes only. Decode mask: $FE0001.
{| class="regdef"
{| class="regdef"
|'''Address'''
|'''Address'''
Line 159: Line 182:
|'''Write'''
|'''Write'''
|-
|-
|$3A0001~?, odd bytes
|$3A0001
|REG_NOSHADOW
|REG_NOSHADOW
|Normal video output
|Normal video output
|-
|-
|$3A0011~?, odd bytes
|$3A0011
|REG_SHADOW
|REG_SHADOW
|[[Video DAC|Darken]] video output
|[[Video DAC|Darken]] video output
|-
|-
|$3A0003~?, odd bytes
|$3A0003
|REG_SWPBIOS
|REG_SWPBIOS
|Use the |BIOS [[Vector_table_swap|vector table]]
|Use the |BIOS [[Vector_table_swap|vector table]]
|-
|-
|$3A0013~?, odd bytes
|$3A0013
|REG_SWPROM
|REG_SWPROM
|Use the cart's vector table
|Use the cart's vector table
|-
|-
|$3A0005~?, odd bytes
|$3A0005
|REG_CRDUNLOCK1
|REG_CRDUNLOCK1
|Enable writes to memory card (use REG_CRDUNLOCK2 too)
|Enable writes to memory card (use REG_CRDUNLOCK2 too)
|-
|-
|$3A0015~?, odd bytes
|$3A0015
|REG_CRDLOCK1
|REG_CRDLOCK1
|Disable writes to memory card
|Disable writes to memory card
|-
|-
|$3A0007~?, odd bytes
|$3A0007
|REG_CRDLOCK2
|REG_CRDLOCK2
|Disable writes to memory card
|Disable writes to memory card
|-
|-
|$3A0017~?, odd bytes
|$3A0017
|REG_CRDUNLOCK2
|REG_CRDUNLOCK2
|Enable writes to memory card (use REG_CRDUNLOCK1 too)   
|Enable writes to memory card (use REG_CRDUNLOCK1 too)   
|-
|-
|$3A0009~?, odd bytes
|$3A0009
|REG_CRDREGSEL
|REG_CRDREGSEL
|Enable "Register select" for memory card
|Enable "Register select" for memory card
|-
|-
|$3A0019~?, odd bytes
|$3A0019
|REG_CRDNORMAL
|REG_CRDNORMAL
|Disable "Register select" for memory card
|Disable "Register select" for memory card
|-
|-
|$3A000B~?, odd bytes
|$3A000B
|REG_BRDFIX
|REG_BRDFIX
|Use the embedded [[SFIX]] and [[SM1]] ROM
|Use the embedded [[SFIX]] and [[SM1]] ROM
|-
|-
|$3A001B~?, odd bytes
|$3A001B
|REG_CRTFIX
|REG_CRTFIX
|Use the cart's [[S ROM]] and [[M1 ROM]]
|Use the cart's [[S ROM]] and [[M1 ROM]]
|-
|-
|$3A000D~?, odd bytes
|$3A000D
|REG_SRAMLOCK
|REG_SRAMLOCK
|Write-protects [[backup RAM]] (MVS)
|Write-protects [[backup RAM]] (MVS)
|-
|-
|$3A001D~?, odd bytes
|$3A001D
|REG_SRAMULOCK
|REG_SRAMULOCK
|Unprotects backup RAM (MVS)
|Unprotects backup RAM (MVS)
|-
|-
|$3A000F~?, odd bytes
|$3A000F
|REG_PALBANK1
|REG_PALBANK1
|Use palette bank 1
|Use palette bank 1
|-
|-
|$3A001F~?, odd bytes
|$3A001F
|REG_PALBANK0
|REG_PALBANK0
|Use palette bank 0
|Use palette bank 0
Line 227: Line 250:
==Video registers==
==Video registers==


Handled by the [[GPU]]s. Byte writes only work on even addresses and stores the same data in the MSB and LSB. Odd addresses aren't mapped ?
Handled by the [[GPU]]s. Byte writes only work on even addresses and stores the same data in the MSB and LSB. Odd addresses aren't mapped ? Decode mask: $FE0001.


{| class="regdef"
{| class="regdef"
Line 564: Line 587:
|?
|?
|}
|}
=About decode masks=
Decode masks aren't verified !
Decode masks can be used to guess which register will be mapped to an address, they can be seen as a mirroring range notation.
A "1" bit means that the corresponding address line is involved in decoding, a "0" bit means it can be anything.
For example, {{Reg|REG_P1CNT}}'s base is $300000 and its mask is $FE0001:
<pre>
BASE 00110000 00000000 00000000
MASK 11111110 00000000 00000001
    0011000x xxxxxxxx xxxxxxx0
</pre>
This means that it should also be accessible at $300002, $300004, $300006... $310002.


[[Category:Base system]]
[[Category:Base system]]
[[Category:Code]]
[[Category:Code]]

Revision as of 11:25, 5 March 2016

Register descriptions

I/O registers

Address Decode mask Name Read Write Handled by
$300000 $FE0001 REG_P1CNT Player 1 controls or trackball data (active low)
Bit 7 6 5 4 3 2 1 0
Def D CBARightLeftDownUp
? NEO-C1
$300001 $FE0081 REG_DIPSW Hardware DIPs (active low)
Bit 7 6 5 4 3 2 1 0
Def Freeze FreeplayEnable Multiplayer configurationCommunication identification code0:Normal controller
1:Mahjong keyboard		0:One coin chute
1:Two coin chutes		Settings mode
Kick watchdog NEO-F0 (read), NEO-B1 (write)
$300081 $FE0081 REG_SYSTYPE IN01 to D7 (test switch) and TYPE to D6, see NEO-F0 ? NEO-F0
$320000 $FE0001 REG_SOUND Read Z80 reply code Send command to Z80 NEO-C1
$320001 $FE0001 REG_STATUS_A Switch inputs are active low
Bit 7 6 5 4 3 2 1 0
Def NEC D4990 data bit NEC D4990 time pulse0:4SLOT
1:6SLOT		Coin-in 4Coin-in 3ServiceCoin-in 2Coin-in 1
? NEO-F0
$340000 $FE0001 REG_P2CNT Player 2 controls (active low)
Bit 7 6 5 4 3 2 1 0
Def D CBARightLeftDownUp
? NEO-C1
$380000 $FE0001 REG_STATUS_B Aux inputs (active low)
Bit 7 6 5 4 3 2 1 0
Def 0:AES
1:MVS		 Memory card
write protected		Memory card
inserted if 00		Select P2Start P2Select P1Start P1
? NEO-C1
$380001 $FE0071 REG_POUTPUT ? Joypad ports outputs
Bit 7 6 5 4 3 2 1 0
Def ? P2 outputsP1 outputs
NEO-D0
$380011 $FE0071 REG_CRDBANK ?
Bit 7 6 5 4 3 2 1 0
Def Memory card bank selection
NEO-D0
$380021 $FE00F1 REG_SLOT ?
Bit 7 6 5 4 3 2 1 0
Def ? Slot #

(Mirror of REG_POUTPUT on the AES)

NEO-F0
$380031 $FE00F1 REG_LEDLATCHES ?
Bit 7 6 5 4 3 2 1 0
Def ? Latch LED2 dataLatch LED1 dataLatch EL panel data?

LED data is latched on 1 to 0 transition.

NEO-F0
$380041 $FE00F1 REG_LEDDATA ? 8-bit data for LEDs and EL panel. See MV-LED. NEO-F0
$380051 $FE00F1 REG_RTCCTRL ? MAME upd4990a_control_16_w (Calendar)
Bit 7 6 5 4 3 2 1 0
Def D4990 StrobeD4990 ClockD4990 DIN
NEO-F0
$380061 $FE0071 REG_RESETCC1 ? Any, coin counter 1 floats NEO-I0
$380063 $FE0071 REG_RESETCC2 ? Any, coin counter 2 floats NEO-I0
$380065 $FE0071 REG_RESETCL1 ? Any, coin lockout 1 floats NEO-I0
$380067 $FE0071 REG_RESETCL2 ? Any, coin lockout 2 floats NEO-I0
$3800D1 $FE0071 ? REG_RTCOUT Write to RTC

uPD4990AWrite(byteValue & 2, byteValue & 4, byteValue & 1);

NEO-F0
$3800E1 $FE0071 REG_SETCC1 ? Any, coin counter 1 sinks current NEO-I0
$3800E3 $FE0071 REG_SETCC2 ? Any, coin counter 2 sinks current NEO-I0
$3800E5 $FE0071 REG_SETCL1 ? Any, coin lockout 1 sinks current NEO-I0
$3800E7 $FE0071 REG_SETCL2 ? Any, coin lockout 2 sinks current NEO-I0

System registers

Handled by a 74HC259 adressable latch on cart systems. Byte writes only. Decode mask: $FE0001.

Address Name Write
$3A0001 REG_NOSHADOW Normal video output
$3A0011 REG_SHADOW Darken video output
$3A0003 REG_SWPBIOS BIOS vector table
$3A0013 REG_SWPROM Use the cart's vector table
$3A0005 REG_CRDUNLOCK1 Enable writes to memory card (use REG_CRDUNLOCK2 too)
$3A0015 REG_CRDLOCK1 Disable writes to memory card
$3A0007 REG_CRDLOCK2 Disable writes to memory card
$3A0017 REG_CRDUNLOCK2 Enable writes to memory card (use REG_CRDUNLOCK1 too)
$3A0009 REG_CRDREGSEL Enable "Register select" for memory card
$3A0019 REG_CRDNORMAL Disable "Register select" for memory card
$3A000B REG_BRDFIX Use the embedded SFIX and SM1 ROM
$3A001B REG_CRTFIX Use the cart's S ROM and M1 ROM
$3A000D REG_SRAMLOCK Write-protects backup RAM (MVS)
$3A001D REG_SRAMULOCK Unprotects backup RAM (MVS)
$3A000F REG_PALBANK1 Use palette bank 1
$3A001F REG_PALBANK0 Use palette bank 0


Video registers

Handled by the GPUs. Byte writes only work on even addresses and stores the same data in the MSB and LSB. Odd addresses aren't mapped ? Decode mask: $FE0001.

Address Name Read Write
$3C0000 REG_VRAMADDR Read VRAM (address isn't changed) Sets VRAM address
$3C0002 REG_VRAMRW Read VRAM (address isn't changed) Write VRAM
$3C0004 REG_VRAMMOD Reads VRAM address modulo Sets VRAM address modulo (signed)
$3C0006 REG_LSPCMODE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def Raster line counter.
See Display timing		 -1:50Hz
0:60Hz (LSPC2 only)		Auto animation counter
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def Auto animation speed
(in frames)		 Timer interrupt
mode		Timer interrupt enableDisable auto animation?
$3C0008 REG_TIMERHIGH Invalid MSBs of timer reload value.
$3C000A REG_TIMERLOW Invalid LSBs of timer reload value.
$3C000C REG_IRQACK Invalid Interrupt Acknowledge (byte !).
Bit 7 6 5 4 3 2 1 0
Def ? Ack VBlankAck HBlankAck IRQ3
$3C000E REG_TIMERSTOP Invalid Bit 0=1: Stops timer counter during first and last 16 lines (32 total) when in PAL mode.


NeoGeo CD registers

NEO-MGA / LC8953 / LC98000 ?

Address Name Size Read Write Handled by
$FF0002 ? Word ? NeoRaine load_files, really interrupt mask ? ?
$FF0004 ? Word ? CDM3-2 BIOS writes 0,1,3,7 ?
$FF0006 ? Word ? CDM3-2 BIOS writes 0x71FF, CDZ writes 0x71FF ?
$FF0008 ? Word ? CDM3-2 BIOS writes 0x0000, CDZ writes 0x0000 ?
$FF000A ? Word ? CDM3-2 BIOS writes 0x7E40, CDZ writes 0x7E00 ?
$FF000E ? Byte ? CDM3-2 BIOS writes $3F,$3C ?
$FF000F ? Byte ? NeoCDIRQUpdate(byteValue);

CDM3-2 BIOS writes $20,$10,$08,$04

?
$FF0011 ? Byte ? CDM3-2 BIOS writes $FE ?
$FF0017 ? Byte nNeoCDMode

CDM3-2 BIOS read/writes bit 0

?
$FF0061 ? Byte ? Bit 6: Execute DMA microcode LC8953
$FF0064~$FF0073 ? (Long)words ? Registers used by microcode (NeoRaine upload_param)
$FF007E~$FF008F ? Words ? Microcode (16x9bit instructions ?)
$FF0101 ? Byte nLC8951Register (4 LSB)

CDM3-2 BIOS writes low nibble

LC8951
$FF0103 ? Byte nLC8951Register value

CDM3-2 BIOS writes 0x10, CDZ writes 0x00 (start up init)

LC8951
$FF0105 ? Byte ? nActiveTransferArea = byteValue

upload_type_w

?
$FF0108 ? Word ? CDM3-2 BIOS writes $5555 ?
$FF010C ? Word ? CDM3-2 BIOS writes $5555 and reads ?
$FF0111 REG_DISBLSPR Byte ? 1=Disable 0=Enable sprites NEO-GRC/NEO-OFC
$FF0115 REG_DISBLFIX Byte ? 1=Disable 0=Enable fix layer
$FF0119 REG_ENVIDEO Byte ? Video output. 1=Enable 0=Disable
$FF011C REG_CDCONFIG Word
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def 1 CD Mech
0:TOP/CDZ
1:FRONT		Lid Status
(Opposite on CDZ)		Configuration
jumpers		?
? NEO-CDD board
$FF0121 REG_UPMAPSPR Byte ? NeoSetSpriteSlot(1);

Set upload zone to SPR DRAM

?
$FF0123 REG_UPMAPPCM Set upload zone to PCM DRAM
$FF0127 REG_UPMAPZ80 Set upload zone to Z80 DRAM
$FF0129 REG_UPMAPFIX Set upload zone to FIX DRAM
$FF0141 REG_UPUNMAPSPR Unset SPR DRAM to upload zone
$FF0143 REG_UPUNMAPPCM Unset PCM DRAM to upload zone
$FF0147 REG_UPUNMAPZ80 Unset Z80 DRAM to upload zone
$FF0149 REG_UPUNMAPFIX Unset FIX DRAM to upload zone
$FF0161 ? ? ? NeoCDCommsRead Status FIFO 10 values (4 bits) ?
$FF0163 ? ? ? NeoCDCommsWrite(byteValue) Command FIFO 10 values (4 bits) ?
$FF0165 ? ? ? NeoCDCommsControl(byteValue & 1, byteValue & 2); (clock,send) ?
$FF016D Byte ? MapVectorTable(!(byteValue == 0xFF)); ?
$FF016F REG_DISBLIRQ Byte ? Disable/enable interrupts nTransferWriteEnable = byteValue ?
$FF0181 Byte ? Enable/Disable (Reset) CD assy ?
$FF0183 REG_ENZ80 Byte ? Enable/Disable (Reset) Z80 ?
$FF0188 REG_CDDALEFTL Word See Reading CDDA sound levels No effect NEO-MGA
$FF018A REG_CDDARIGHTL
$FF01A1 ? Byte ? Upload zone 1MiB SPR DRAM bank selection ?
$FF01A3 ? Byte ? Upload zone 512KiB PCM DRAM bank selection ?
$FF01A7 ? Byte ? CDM3-2 BIOS writes ?
$FF01FC ? Word ? CDDA control ? ?
$FF01FE ? Word ? CD DA/data switch ? ?

About decode masks

Decode masks aren't verified !

Decode masks can be used to guess which register will be mapped to an address, they can be seen as a mirroring range notation.

A "1" bit means that the corresponding address line is involved in decoding, a "0" bit means it can be anything.

For example, REG_P1CNT's base is $300000 and its mask is $FE0001: 

BASE 00110000 00000000 00000000
MASK 11111110 00000000 00000001
     0011000x xxxxxxxx xxxxxxx0

This means that it should also be accessible at $300002, $300004, $300006... $310002.

Retrieved from "https://wiki.neogeodev.org/index.php?title=Memory_mapped_registers&oldid=4706"