Category:Chips: Difference between revisions

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=Needed=
Todo:
*[[NEO-257]],[[NEO-I0]] (pictures)
* Chips with (manufacturer name) need ChipInfo templates on their pages
*[[LC98000]],[[LSPC-A0]],[[PRO-C0]],[[PRO-B0]],[[NEO-DCR-T]],[[NEO-SDR-T]] (pages)
* [[LC98000]], [[LSPC-A0]], [[PRO-C0]], [[PRO-B0]], [[NEO-GRC2]], [[NEO-MGA]] pinouts
*RAMs (VRAM, 68k, Z80)
* RAMs (VRAM, 68k, Z80)
*All SNK CD chips
 
=SNK chips, both cart and CD systems=


{| align=center class="regdef"
{| align=center class="regdef"
|rowspan="2"|'''Picture'''
|'''Picture'''
|rowspan="2"|'''Reference'''
|'''Reference'''
|rowspan="2"|'''Description'''
|'''Description'''
|colspan="5"|'''Found in'''
|'''Found in'''
|- style="background-color:AllEEE;"
|'''CD1'''
|'''CD2'''
|'''CDZ'''
|'''Pinout'''
|'''Pinout'''
|-
|[[File:cd2_buf.jpg|x128px|center]]
|[[NEO-BUF]]
|Dual 8-bit bidirectional buffer
|All
|All
|?
|[[File:neo-buf_pinout.png|x128px|center]]
|-
|[[File:brd_grz.jpg|x128px|center]]
|[[NEO-GRZ]]
|Graphics chip
|
|
|?
|
|-
|[[File:brd_ysa2.jpg|x128px|center]]
|[[NEO-YSA2]]
|Audio subsystem chip
|
|
|All
|
|}
=SNK chips, AES/MVS=
{| align=center class="regdef"
|rowspan="2"|'''Picture'''
|rowspan="2"|'''Reference'''
|rowspan="2"|'''Description'''
|colspan="5"|'''Found in'''
|- style="background-color:AllEEE;"
|'''AES'''
|'''MVS'''
|Pinout
|-
|-
|[[File:mvs_lspc-a0.jpg|x128px|center]]
|[[File:mvs_lspc-a0.jpg|x128px|center]]
|[[LSPC-A0]]
|[[LSPC-A0]]
|First generation graphics chip
|First generation graphics chip
|Some
|Some AES, some MVS
|Some
|[[File:LSPC-A0_pinout.png|x128px|center]]
|
|-
|-
|[[File:aes_lspc2a2.jpg|x128px|center]]
|[[File:aes_lspc2a2.jpg|x128px|center]]
|[[LSPC2-A2]]
|[[LSPC2-A2]]
|Second generation graphics chip
|Second generation graphics chip
|Some
|Some AES, some MVS
|Some
|[[File:LSPC2-A2_pinout.png|x128px|center]]
|[[File:Lspc2-a2_pinout.png|x128px|center]]
|-
|[[File:Lspc2-a3.jpg|x128px|center]]
|[[LSPC2-A3]]
|Revision of the second generation graphics chip
|Some MVS
|[[File:LSPC2-A2_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_257.jpg|x128px|center]]
|[[File:neo-244.jpg|x128px|center]]
|[[NEO-257]] (QFP64R)
|[[NEO-244]]
|Quad 74HC257
|
|
|Some
|Some MVS
|[[File:neo-257_pinout.png|x128px|center]]
|[[File:NEO-244_pinout.png|x128px|center]]
|-
|[[File:neo-253.jpg|x128px|center]]
|[[NEO-253]]
|Quint 74HC253, 4-to-1 multiplexers
|Some MVS
|[[File:neo-253_pinout.png|x128px|center]]
|-
|[[File:neo-257.jpg|x128px|center]]
|[[NEO-257]]
|Quad 74HC257, 2-to-1 multiplexers
|Some MVS
|[[File:neo-257_L4_pinout.png|x128px|center]]
|-
|[[File:crt_273.jpg|x128px|center]]
|[[NEO-273]]
|C and [[S ROM]] address latches
|Cartridges
|[[File:NEO-273_pinout.png|x128px|center]]
|-
|-
|[[File:aes_b1.jpg|x128px|center]]
|[[File:aes_b1.jpg|x128px|center]]
Line 82: Line 59:
*Line buffers
*Line buffers
*Palette arbiter
*Palette arbiter
|Some
|Some AES, some MVS
|Some
|[[File:NEO-B1_pinout.png|x128px|center]]
|[[File:neo-b1_pinout.png|x128px|center]]
|-
|[[File:cd2_buf.jpg|x128px|center]]
|[[NEO-BUF]]
|Dual 8-bit bidirectional buffer
|CD1, CD2, some late MVS
|[[File:NEO-BUF_pinout.png|x128px|center]]
|-
|-
|[[File:aes_c1.jpg|x128px|center]]
|[[File:aes_c1.jpg|x128px|center]]
Line 91: Line 73:
*Address decoder
*Address decoder
*Joystick inputs
*Joystick inputs
|Some
*[[Z80]] interface
|Some
|Some AES, some MVS
|[[File:neo-c1_pinout.png|x128px|center]]
|[[File:NEO-C1_pinout.png|x128px|center]]
|-
|-
|[[File:aes_d0.jpg|x128px|center]]
|[[File:aes_d0.jpg|x128px|center]]
|[[NEO-D0]] (QFP64R)
|[[NEO-D0]]
|Audio subsystem controller
|
|Some
*Audio subsystem controller
|Some
*Output port
|[[File:neo-d0_pinout.png|x128px|center]]
*[[Memory card]] bankswitching
|All AES ?, some MVS
|[[File:NEO-D0_pinout.png|x128px|center]]
|-
|-
|[[File:brd_dcr-t.jpg|x128px|center]]
|[[File:crt_cmc.jpg|x128px|center]]
|[[NEO-DCR-T]]
|[[NEO-CMC]]
|?
|
|Some
|
|
*NEO-273 logic
*NEO-ZMC logic
*NEO-ZMC2 logic
*C+S ROM decryption
*C/S ROM multiplexer
*S ROM bankswitching
*M ROM decryption (NEOCMC50 only)
*M ROM bankswitching
|Some AES, some MVS
|[[File:Neocmc_7050_7042_pinout.png|x200px|center]]
|-
|-
|[[File:mvs_sdr-t.jpg|x128px|center]]
|[[File:neo-dcr-t.jpg|x128px|center]]
|[[NEO-SDR-T]]
|[[NEO-DCR-T]]
|?
|
|Some
|
|
* Address decoding
* Coin I/O
* [[Memory_mapped_registers#System_registers|System register]]
* [[Wait cycle]] generator
|Some MVS
|[[File:NEO-DCR_pinout.png|x128px|center]]
|-
|-
|[[File:aes_e0.jpg|x128px|center]]
|[[File:aes_e0.jpg|x128px|center]]
|[[NEO-E0]] (QFP64R)
|[[NEO-E0]]
|
|
*Vector table swapping
*Vector table swapping
*Memory card address translation
*Buffer/driver
|Some
|Some AES, some MVS
|Some
|[[File:NEO-E0_pinout.png|x128px|center]]
|[[File:neo-e0_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_f0.jpg|x128px|center]]
|[[File:mvs_f0.jpg|x128px|center]]
|[[NEO-F0]] (QFP64R)
|[[NEO-F0]]
|
|
*Calendar access
*Calendar access
Line 132: Line 125:
*LED marquee outputs
*LED marquee outputs
*Slot selection
*Slot selection
|
|Some MVS
|Some
|[[File:NEO-F0_pinout.png|x128px|center]]
|[[File:neo-f0_pinout.png|x128px|center]]
|-
|-
|[[File:aes_g0.jpg|x128px|center]]
|[[File:aes_g0.jpg|x128px|center]]
|[[NEO-G0]] (QFP64R)
|[[NEO-G0]]
|
|
AES specific ?
Quad 245 bidirectional buffer.
*Palette data buffer
*Palette data buffer
*Memory card data buffer
*Memory card data buffer
|Some
*[[68k]] data bus buffer
|Some
|All AES, some MVS ?
|[[File:neo-g0_pinout.png|x128px|center]]
|[[File:NEO-G0_pinout.png|x128px|center]]
|-
|[[File:cd2_grc.jpg|x128px|center]]
|[[NEO-GRC]]
|Graphics chip
|All CD1, all CD2
|[[File:Neo-grc_pinout.png|x128px|center]]
|-
|[[File:neo-grc2-f.jpg|x128px|center]]
|[[NEO-GRC2-F]] (Fujitsu)
|Graphics chip
|All CDZ ?, Some MVS
|[[File:neo-grc2_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_zmc2.jpg|x128px|center]]
|[[File:brd_grz.jpg|x128px|center]]
|[[NEO-ZMC2]] (QFP80R)
|[[NEO-GRZ]] (Fujitsu)
|All-in-one [[GPU]]
|ROM-only
|
|
*Z80 Memory Controller
*Tile serializer
|Carts
|Some
|[[File:neo-zmc2_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_pro-b0.jpg|x128px|center]]
|[[File:neo-i0.jpg|x128px|center]]
|[[PRO-B0]]
|[[NEO-I0]]
|First generation graphics chip
|Multi-purpose MVS specific chip.
|Some
*[[SFIX ROM]] address latch
|Some
*Coin counter and lockout outputs
|
|Some MVS
|[[File:NEO-I0_pinout.png|x128px|center]]
|-
|[[File:cd2_mga.jpg|x128px|center]]
|[[NEO-MGA]]<br>[[NEO-MGA-T]]<br>[[NEO-MGA-T2]]
|CD unit interface, latches, address decoding ?
|All CD1, all CD2, all CDZ, some MVS
|[[File:Neo-mga_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_pro-c0.jpg|x128px|center]]
|[[File:cd2_ofc.jpg|x128px|center]]
|[[PRO-C0]]
|[[NEO-OFC]] (Fujitsu)
|?
|Graphics chip
|Some
|All CD1, all CD2
|Some
|
|
|-
|-
|[[File:mvs_pro-ct0.jpg|x128px|center]]
|[[File:brd_pcm2.jpg|x128px|center]]
|[[PRO-CT0]] (DIP64)
|[[NEO-PCM2]] (Fujitsu)
|[[C ROM]] serializer and multiplexer
|Carts
|Some
|
|
|}
*[[PCM]]
 
*[[P ROM]] decoding, bankswitching and decryption
 
|ROM-only boards
=Cartridge chips=
|[[File:neo-pcm2_pinout.png|x128px|center]]
 
{| align=center class="regdef"
|'''Picture'''
|'''Reference'''
|'''Description'''
|'''Pinout'''
|-
|-
|[[File:crt_hd6301.jpg|x128px|center]]
|[[File:neo-sdr-t.jpg|x128px|center]]
|[[HD6301]] (DIP40)
|[[NEO-SDR-T]]
|Microcontroller
|
|
* Joypad I/O
* Z80 address and port decoding
* 68k/Z80 communication latches and interrupt generation
|Some MVS, All [[Neo Print]]s
|[[File:NEO-SDR_pinout.png|x128px|center]]
|-
|-
|[[File:crt_273.jpg|x128px|center]]
|[[File:cd2_sft.jpg|x128px|center]]
|[[NEO-273]] (QFP64R)
|[[NEO-SFT]] (Fujitsu)
|C and [[S ROM]] address latch
|Graphics related
|[[File:neo-273_pinout.png|x128px|center]]
|All CD1, all CD2
|-
|[[File:crt_cmc.jpg|x128px|center]]
|[[NEO-CMC]]
|
*NEO-273 logic
*C ROM decryption
*C/S ROM multiplexer
*S ROM bankswitching
|
|
|-
|-
|[[File:crt_pcm.jpg|x128px|center]]
|[[File:cd2_sud.jpg|x128px|center]]
|[[PCM]] (QFP80R)
|[[NEO-SUD]]
|Z80 subsystem controler
|All CD1, all CD2
|
|
*ADPCM bus latches
*[[V ROM]] multiplexer
|[[File:pcm_pinout.png|x128px|center]]
|-
|-
|[[File:brd_pcm2.jpg|x128px|center]]
|[[File:cd2_voc.jpg|x128px|center]]
|[[NEO-PCM2]]
|[[NEO-VOC]] (Yamaha)
|
|PCM memory handler
*[[NEO-PCM]]
|All CD1, all CD2
*[[P ROM]] decoding, bankswitching and decryption
|
|
|-
|-
|[[File:brd_pvc.jpg|x128px|center]]
|[[File:cd2_ysa.jpg|x128px|center]]
|[[NEO-PVC]]
|[[NEO-YSA]] (Yamaha)
|[[P ROM]] decryption chip
|Audio subsystem chip
|Some CD2
|
|
|-
|-
|[[File:crt_sma.jpg|x128px|center]]
|[[File:brd_ysa2.jpg|x128px|center]]
|[[NEO-SMA]]
|[[NEO-YSA2]] (Yamaha)
|[[P ROM]] decryption chip
|Complete audio subsystem chip and controller inputs
|
*Embedded Z80+RAM
*Embedded YM2610
|Some MVS, CDZ, All ROM-only
|[[File:NEO-YSA2_pinout.png|x128px|center]]
|-
|-
|[[File:crt_zmc.jpg|x128px|center]]
|[[File:crt_zmc.jpg|x128px|center]]
|[[NEO-ZMC]] (SOIC24)
|[[NEO-ZMC]]
|Z80 Memory Controller
|Z80 Memory Controller
|[[File:neo-zmc_pinout.png|x128px|center]]
|Cartridges
|[[File:NEO-ZMC_pinout.png|x128px|center]]
|-
|-
|[[File:crt_snk-9201.jpg|x128px|center]]
|[[File:mvs_zmc2.jpg|x128px|center]]
|[[SNK-9201]] (DIP64)
|[[NEO-ZMC2]]
|[[P ROM]] protection chip
|
|
|}
*Z80 Memory Controller
 
*Sprite tile serializer
 
|AES carts, some MVS
=SNK chips, CD only=
|[[File:NEO-ZMC2_pinout.png|x128px|center]]
 
{| align=center class="regdef"
|rowspan="2"|'''Picture'''
|rowspan="2"|'''Reference'''
|rowspan="2"|'''Description'''
|colspan="5"|'''Found in'''
|- style="background-color:AllEEE;"
|'''CD1'''
|'''CD2'''
|'''CDZ'''
|'''Pinout'''
|-
|-
|[[File:cd2_grc.jpg|x128px|center]]
|[[File:crt_pcm.jpg|x128px|center]]
|[[NEO-GRC]]
|[[PCM]]
|Graphics chip
|All
|All
|?
|
|
*ADPCM bus latches
*[[V ROM]] multiplexer
|Cartridges
|[[File:PCM_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_mga.jpg|x128px|center]]
|[[File:pstg-snk.jpg|x128px|center]]
|[[NEO-MGA]]<br>NEO-MGA-T<br>NEO-MGA-T2
|[[PSTG-SNK]]
|CD unit interface
|
|All
[[Neo Print]] GPU.
|All
|All
|
|
|-
|[[File:cd2_ofc.jpg|x128px|center]]
|[[NEO-OFC]]
|Graphics chip
|All
|All
|?
|
|
|-
|-
|[[File:cd2_sft.jpg|x128px|center]]
|[[File:mvs_pro-b0.jpg|x128px|center]]
|[[NEO-SFT]]
|[[PRO-B0]]
|Graphics related
|First generation
|All
*Palette arbiter
|All
*Z80 latch
|?
|Some AES, some MVS
|
|[[File:PRO-B0_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_sud.jpg|x128px|center]]
|[[File:mvs_pro-c0.jpg|x128px|center]]
|[[NEO-SUD]]
|[[PRO-C0]]
|Z80 subsystem controler
|First generation
|All
*Address decoder
|All
*Glue
|?
*Line buffer
|[[File:neo-sud_pinout.png|x128px|center]]
*Palette arbiter
|Some AES, some MVS
|[[File:PRO-C0_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_voc.jpg|x128px|center]]
|[[File:mvs_pro-ct0.jpg|x64px|center]]
|[[NEO-VOC]]
|[[PRO-CT0]]
|PCM memory handler
|[[C ROM]] character serializer and multiplexer
|All
|Some AES carts, some MVS
|All
|[[File:pro-ct0_pinout.png|x128px|center]]
|?
|[[File:neo-voc_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_ysa.jpg|x128px|center]]
|[[File:brd_pvc.jpg|x128px|center]]
|[[NEO-YSA]]
|[[NEO-PVC]] (Fujitsu)
|Audio subsystem chip
|[[P ROM]] decryption chip
|
|
|
|Some
|-
|[[File:crt_sma.jpg|x128px|center]]
|[[NEO-SMA]]
|[[P ROM]] decryption chip
|
|
|
|
|}
|}


=Other chips=
=Other chips=
Line 327: Line 306:
|-
|-
|[[File:aes_68k.jpg|x128px|center]]
|[[File:aes_68k.jpg|x128px|center]]
|[[68k|68HC000]] (DIP64)
|[[68k|68HC000]] (Toshiba DIP64)
|rowspan="2"|16bit CPU  
|rowspan="2"|16bit CPU  
|All
|All
Line 336: Line 315:
|-
|-
|[[File:cd2_68k.jpg|x128px|center]]
|[[File:cd2_68k.jpg|x128px|center]]
|[[68k|68HC000]] (PLCC68)
|[[68k|68HC000]] (Motorola PLCC68)
|
|
|Some
|Some
Line 359: Line 338:
|All
|All
|?
|?
|-
|[[File:crt_hd6301.jpg|x128px|center]]
|Hitachi [[HD6301]] (DIP40)
|Microcontroller
|colspan="5"|[[Multiplayer]] cartridges
|-
|-
|[[File:cd2_lc78815.jpg|x128px|center]]
|[[File:cd2_lc78815.jpg|x128px|center]]
Line 397: Line 381:
|-
|-
|[[File:mvs_upd4990.jpg|x128px|center]]
|[[File:mvs_upd4990.jpg|x128px|center]]
|Nec [[UPD4990]]
|NEC [[UPD4990]]
|Real Time Clock
|Real Time Clock
|
|
Line 424: Line 408:
|-
|-
|[[File:aes_z80.jpg|x128px|center]]
|[[File:aes_z80.jpg|x128px|center]]
|[[z80]] (DIP40)
|Zilog [[z80]] (DIP40)
|rowspan="2"|8bit CPU
|rowspan="2"|8bit CPU
|All
|All
Line 433: Line 417:
|-
|-
|[[File:cd2_z80.jpg|x128px|center]]
|[[File:cd2_z80.jpg|x128px|center]]
|[[z80]] (SOIC)
|Toshiba [[z80]] (SOIC)
|
|
|Some
|Some
Line 457: Line 441:
|[[File:mvs_sp-s2.jpg|x128px|center]]
|[[File:mvs_sp-s2.jpg|x128px|center]]
|SP-S2
|SP-S2
|MVS [[BIOSes|BIOS]]
|MVS [[System ROM]]
|rowspan="3"|MVS systems
|rowspan="3"|MVS systems
|-
|-
Line 465: Line 449:
|-
|-
|[[File:mvs_sfix.jpg|x128px|center]]
|[[File:mvs_sfix.jpg|x128px|center]]
|[[SFIX]]
|[[SFIX ROM]]
|Embedded [[Fix layer|Fix]] ROM
|Embedded [[Fix layer|Fix]] ROM
|-
|-
|[[File:aes_biosep0.jpg|x128px|center]]
|[[File:aes_biosep0.jpg|x128px|center]]
|[[NEO-EP0]]
|[[NEO-EP0]]
|AES BIOS
|AES System ROM
|AES systems
|AES systems
|-
|-
|[[File:cd2_top-sp1-1.jpg|x128px|center]]
|Picture needed
|TOP-SP1-1
|TOP-SP1-1
|CD2 BIOS
|CD2 System ROM
|Top loading CD systems (LC8953 versions)
|Top loading CD systems (LC8953 versions)
|-
|-
|[[File:cd2_top-sp1-2.jpg|128px|center]]
|Picture needed
|TOP-SP1-2
|TOP-SP1-2
|CD2 BIOS
|CD2 System ROM
|Top loading CD systems (LC98000 versions)
|Top loading CD systems (LC98000 versions)
|-
|-
|[[File:cd1_front-sp1.jpg|128px|center]]
|[[File:cd1_front-sp1.jpg|128px|center]]
|FRONT-SP1
|FRONT-SP1
|CD1 BIOS
|CD1 System ROM
|Front loading CD systems
|Front loading CD systems
|}
|}

Latest revision as of 06:58, 27 July 2023

Todo:

Picture Reference Description Found in Pinout
LSPC-A0 First generation graphics chip Some AES, some MVS
LSPC2-A2 Second generation graphics chip Some AES, some MVS
LSPC2-A3 Revision of the second generation graphics chip Some MVS
NEO-244 Some MVS
NEO-253 Quint 74HC253, 4-to-1 multiplexers Some MVS
NEO-257 Quad 74HC257, 2-to-1 multiplexers Some MVS
NEO-273 C and S ROM address latches Cartridges
NEO-B1 Second generation graphics chip
  • Sprite and FIX multiplexer
  • Line buffers
  • Palette arbiter
 Some AES, some MVS
NEO-BUF Dual 8-bit bidirectional buffer CD1, CD2, some late MVS
NEO-C1
  • Address decoder
  • Joystick inputs
  • Z80 interface
 Some AES, some MVS
NEO-D0
  • Audio subsystem controller
  • Output port
  • Memory card bankswitching
 All AES ?, some MVS
NEO-CMC
  • NEO-273 logic
  • NEO-ZMC logic
  • NEO-ZMC2 logic
  • C+S ROM decryption
  • C/S ROM multiplexer
  • S ROM bankswitching
  • M ROM decryption (NEOCMC50 only)
  • M ROM bankswitching
 Some AES, some MVS
NEO-DCR-T Some MVS
NEO-E0
  • Vector table swapping
  • Buffer/driver
 Some AES, some MVS
NEO-F0
  • Calendar access
  • Dip/cab switches, coin counters
  • LED marquee outputs
  • Slot selection
 Some MVS
NEO-G0

Quad 245 bidirectional buffer.

  • Palette data buffer
  • Memory card data buffer
  • 68k data bus buffer
 All AES, some MVS ?
NEO-GRC Graphics chip All CD1, all CD2
NEO-GRC2-F (Fujitsu) Graphics chip All CDZ ?, Some MVS
NEO-GRZ (Fujitsu) All-in-one GPU ROM-only
NEO-I0 Multi-purpose MVS specific chip.
  • SFIX ROM address latch
  • Coin counter and lockout outputs
 Some MVS
NEO-MGA
NEO-MGA-T
NEO-MGA-T2 		CD unit interface, latches, address decoding ? All CD1, all CD2, all CDZ, some MVS
NEO-OFC (Fujitsu) Graphics chip All CD1, all CD2
NEO-PCM2 (Fujitsu)
  • PCM
  • P ROM decoding, bankswitching and decryption
 ROM-only boards
NEO-SDR-T
  • Joypad I/O
  • Z80 address and port decoding
  • 68k/Z80 communication latches and interrupt generation
 Some MVS, All Neo Prints
NEO-SFT (Fujitsu) Graphics related All CD1, all CD2
NEO-SUD Z80 subsystem controler All CD1, all CD2
NEO-VOC (Yamaha) PCM memory handler All CD1, all CD2
NEO-YSA (Yamaha) Audio subsystem chip Some CD2
NEO-YSA2 (Yamaha) Complete audio subsystem chip and controller inputs
  • Embedded Z80+RAM
  • Embedded YM2610
 Some MVS, CDZ, All ROM-only
NEO-ZMC Z80 Memory Controller Cartridges
NEO-ZMC2
  • Z80 Memory Controller
  • Sprite tile serializer
 AES carts, some MVS
PCM
  • ADPCM bus latches
  • V ROM multiplexer
 Cartridges
PSTG-SNK

Neo Print GPU.

PRO-B0 First generation
  • Palette arbiter
  • Z80 latch
 Some AES, some MVS
PRO-C0 First generation
  • Address decoder
  • Glue
  • Line buffer
  • Palette arbiter
 Some AES, some MVS
PRO-CT0 C ROM character serializer and multiplexer Some AES carts, some MVS
NEO-PVC (Fujitsu) P ROM decryption chip
NEO-SMA P ROM decryption chip

Other chips

Picture Reference Description Found in
AES MVS CD1 CD2 CDZ
68HC000 (Toshiba DIP64) 16bit CPU All Some
68HC000 (Motorola PLCC68) Some All All All
Sony CXA1145 RGB encoder All
Sony CXA1645 ? All ?
Hitachi HD6301 (DIP40) Microcontroller Multiplayer cartridges
Sanyo LC78815 Stereo DAC ? All
Sanyo LC89515 CD host and error corrector All All ?
Sanyo LC8953 PUPPET All Some ?
Sanyo LC98000 PUPPET replacement Some ?
NEC UPD4990 Real Time Clock All
Yamaha YM2610 Sound synthesizer All All All Some
Yamaha YM3016 Audio DAC All All All Some
Zilog z80 (DIP40) 8bit CPU All Some
Toshiba z80 (SOIC) Some All All All


Memory chips

Picture Reference Description Found in
LO Shrink lookup ROM All systems
SP-S2 MVS System ROM MVS systems
SM1 Embedded sound driver ROM
SFIX ROM Embedded Fix ROM
NEO-EP0 AES System ROM AES systems
Picture needed TOP-SP1-1 CD2 System ROM Top loading CD systems (LC8953 versions)
Picture needed TOP-SP1-2 CD2 System ROM Top loading CD systems (LC98000 versions)
FRONT-SP1 CD1 System ROM Front loading CD systems

Subcategories

This category has only the following subcategory.

C

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