Category:Chips: Difference between revisions

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=Needed=
Todo:
*[[LC98000]],[[LSPC-A0]],[[PRO-C0]],[[PRO-B0]],[[NEO-DCR-T]],[[NEO-SDR-T]] (pages)
* Chips with (manufacturer name) need ChipInfo templates on their pages
*RAMs (VRAM, 68k, Z80)
* [[LC98000]], [[LSPC-A0]], [[PRO-C0]], [[PRO-B0]], [[NEO-GRC2]], [[NEO-MGA]] pinouts
*All SNK CD chips
* RAMs (VRAM, 68k, Z80)


{| align=center class="regdef"
{| align=center class="regdef"
Line 12: Line 12:
|-
|-
|[[File:mvs_lspc-a0.jpg|x128px|center]]
|[[File:mvs_lspc-a0.jpg|x128px|center]]
|[[LSPC-A0]] (QFP160)
|[[LSPC-A0]]
|First generation graphics chip
|First generation graphics chip
|Some AES, some MVS
|Some AES, some MVS
|[[File:Lspc-a0_pinout.png|x128px|center]]
|[[File:LSPC-A0_pinout.png|x128px|center]]
|-
|-
|[[File:aes_lspc2a2.jpg|x128px|center]]
|[[File:aes_lspc2a2.jpg|x128px|center]]
Line 21: Line 21:
|Second generation graphics chip
|Second generation graphics chip
|Some AES, some MVS
|Some AES, some MVS
|[[File:Lspc2-a2_pinout.png|x128px|center]]
|[[File:LSPC2-A2_pinout.png|x128px|center]]
|-
|[[File:Lspc2-a3.jpg|x128px|center]]
|[[LSPC2-A3]]
|Revision of the second generation graphics chip
|Some MVS
|[[File:LSPC2-A2_pinout.png|x128px|center]]
|-
|[[File:neo-244.jpg|x128px|center]]
|[[NEO-244]]
|
|Some MVS
|[[File:NEO-244_pinout.png|x128px|center]]
|-
|[[File:neo-253.jpg|x128px|center]]
|[[NEO-253]]
|Quint 74HC253, 4-to-1 multiplexers
|Some MVS
|[[File:neo-253_pinout.png|x128px|center]]
|-
|-
|[[File:neo-257.jpg|x128px|center]]
|[[File:neo-257.jpg|x128px|center]]
|[[NEO-257]] (QFP64R)
|[[NEO-257]]
|Quad 74HC257, 2-to-1 multiplexers
|Quad 74HC257, 2-to-1 multiplexers
|Some MVS
|Some MVS
Line 30: Line 48:
|-
|-
|[[File:crt_273.jpg|x128px|center]]
|[[File:crt_273.jpg|x128px|center]]
|[[NEO-273]] (QFP64R)
|[[NEO-273]]
|C and [[S ROM]] address latches
|C and [[S ROM]] address latches
|
|Cartridges
|[[File:neo-273_pinout.png|x128px|center]]
|[[File:NEO-273_pinout.png|x128px|center]]
|-
|-
|[[File:aes_b1.jpg|x128px|center]]
|[[File:aes_b1.jpg|x128px|center]]
Line 42: Line 60:
*Palette arbiter
*Palette arbiter
|Some AES, some MVS
|Some AES, some MVS
|[[File:neo-b1_pinout.png|x128px|center]]
|[[File:NEO-B1_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_buf.jpg|x128px|center]]
|[[File:cd2_buf.jpg|x128px|center]]
|[[NEO-BUF]]
|[[NEO-BUF]]
|Dual 8-bit bidirectional buffer
|Dual 8-bit bidirectional buffer
|CD1, CD2
|CD1, CD2, some late MVS
|[[File:neo-buf_pinout.png|x128px|center]]
|[[File:NEO-BUF_pinout.png|x128px|center]]
|-
|-
|[[File:aes_c1.jpg|x128px|center]]
|[[File:aes_c1.jpg|x128px|center]]
Line 57: Line 75:
*[[Z80]] interface
*[[Z80]] interface
|Some AES, some MVS
|Some AES, some MVS
|[[File:neo-c1_pinout.png|x128px|center]]
|[[File:NEO-C1_pinout.png|x128px|center]]
|-
|-
|[[File:aes_d0.jpg|x128px|center]]
|[[File:aes_d0.jpg|x128px|center]]
|[[NEO-D0]] (QFP64R)
|[[NEO-D0]]
|*Audio subsystem controller
|
*Audio subsystem controller
*Output port
*Output port
*[[Memory card]] bankswitching
*[[Memory card]] bankswitching
|All AES ?, some MVS
|All AES ?, some MVS
|[[File:neo-d0_pinout.png|x128px|center]]
|[[File:NEO-D0_pinout.png|x128px|center]]
|-
|-
|[[File:crt_cmc.jpg|x128px|center]]
|[[File:crt_cmc.jpg|x128px|center]]
Line 72: Line 91:
*NEO-273 logic
*NEO-273 logic
*NEO-ZMC logic
*NEO-ZMC logic
*C ROM decryption
*NEO-ZMC2 logic
*C+S ROM decryption
*C/S ROM multiplexer
*C/S ROM multiplexer
*S ROM bankswitching
*S ROM bankswitching
*M ROM decryption (NEOCMC50 only)
*M ROM decryption (NEOCMC50 only)
*M ROM bankswitching
*M ROM bankswitching
|Some cartridges
|Some AES, some MVS
|[[File:Neocmc_7050_7042_pinout.png|x200px|center]]
|[[File:Neocmc_7050_7042_pinout.png|x200px|center]]
|-
|-
|[[File:neo-dcr-t.jpg|x128px|center]]
|[[File:neo-dcr-t.jpg|x128px|center]]
|[[NEO-DCR-T]]
|[[NEO-DCR-T]]
|?
|
* Address decoding
* Coin I/O
* [[Memory_mapped_registers#System_registers|System register]]
* [[Wait cycle]] generator
|Some MVS
|Some MVS
|
|[[File:NEO-DCR_pinout.png|x128px|center]]
|-
|-
|[[File:aes_e0.jpg|x128px|center]]
|[[File:aes_e0.jpg|x128px|center]]
|[[NEO-E0]] (QFP64R)
|[[NEO-E0]]
|
|
*Vector table swapping
*Vector table swapping
*Buffer/driver
*Buffer/driver
|Some AES, some MVS
|Some AES, some MVS
|[[File:neo-e0_pinout.png|x128px|center]]
|[[File:NEO-E0_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_f0.jpg|x128px|center]]
|[[File:mvs_f0.jpg|x128px|center]]
|[[NEO-F0]] (QFP64R)
|[[NEO-F0]]
|
|
*Calendar access
*Calendar access
Line 102: Line 126:
*Slot selection
*Slot selection
|Some MVS
|Some MVS
|[[File:neo-f0_pinout.png|x128px|center]]
|[[File:NEO-F0_pinout.png|x128px|center]]
|-
|-
|[[File:aes_g0.jpg|x128px|center]]
|[[File:aes_g0.jpg|x128px|center]]
|[[NEO-G0]] (QFP64R)
|[[NEO-G0]]
|
|
Quad 245 bidirectional buffer.
Quad 245 bidirectional buffer.
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*[[68k]] data bus buffer
*[[68k]] data bus buffer
|All AES, some MVS ?
|All AES, some MVS ?
|[[File:neo-g0_aes_pinout.png|x128px|center]]
|[[File:NEO-G0_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_grc.jpg|x128px|center]]
|[[File:cd2_grc.jpg|x128px|center]]
Line 118: Line 142:
|Graphics chip
|Graphics chip
|All CD1, all CD2
|All CD1, all CD2
|
|[[File:Neo-grc_pinout.png|x128px|center]]
|-
|-
|[[File:neo-grc2-f.jpg|x128px|center]]
|[[File:neo-grc2-f.jpg|x128px|center]]
|[[NEO-GRC2-F]]
|[[NEO-GRC2-F]] (Fujitsu)
|Graphics chip
|Graphics chip
|Some MVS
|All CDZ ?, Some MVS
|
|[[File:neo-grc2_pinout.png|x128px|center]]
|-
|-
|[[File:brd_grz.jpg|x128px|center]]
|[[File:brd_grz.jpg|x128px|center]]
|[[NEO-GRZ]]
|[[NEO-GRZ]] (Fujitsu)
|All-in-one [[GPU]]
|All-in-one [[GPU]]
|All CDZ ?, ROM-only
|ROM-only
|
|
|-
|-
Line 135: Line 159:
|[[NEO-I0]]
|[[NEO-I0]]
|Multi-purpose MVS specific chip.
|Multi-purpose MVS specific chip.
*[[SFIX]] ROM address latch
*[[SFIX ROM]] address latch
*Coin counter and lockout outputs
*Coin counter and lockout outputs
|Some MVS
|Some MVS
|[[File:neo-i0_pinout.png|x128px|center]]
|[[File:NEO-I0_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_mga.jpg|x128px|center]]
|[[File:cd2_mga.jpg|x128px|center]]
|[[NEO-MGA]]<br>NEO-MGA-T<br>NEO-MGA-T2
|[[NEO-MGA]]<br>[[NEO-MGA-T]]<br>[[NEO-MGA-T2]]
|CD unit interface, latches, address decoding ?
|CD unit interface, latches, address decoding ?
|All CD1, all CD2, all CDZ, some MVS
|All CD1, all CD2, all CDZ, some MVS
|[[File:Neo-mga.png|x128px|center]]
|[[File:Neo-mga_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_ofc.jpg|x128px|center]]
|[[File:cd2_ofc.jpg|x128px|center]]
|[[NEO-OFC]]
|[[NEO-OFC]] (Fujitsu)
|Graphics chip
|Graphics chip
|All CD1, all CD2
|All CD1, all CD2
Line 153: Line 177:
|-
|-
|[[File:brd_pcm2.jpg|x128px|center]]
|[[File:brd_pcm2.jpg|x128px|center]]
|[[NEO-PCM2]]
|[[NEO-PCM2]] (Fujitsu)
|
|
*[[PCM]]
*[[PCM]]
*[[P ROM]] decoding, bankswitching and decryption
*[[P ROM]] decoding, bankswitching and decryption
|
|ROM-only boards
|[[File:neo-pcm2_pinout.png|x128px|center]]
|[[File:neo-pcm2_pinout.png|x128px|center]]
|-
|-
|[[File:neo-sdr-t.jpg|x128px|center]]
|[[File:neo-sdr-t.jpg|x128px|center]]
|[[NEO-SDR-T]]
|[[NEO-SDR-T]]
|?
|Some MVS
|
|
* Joypad I/O
* Z80 address and port decoding
* 68k/Z80 communication latches and interrupt generation
|Some MVS, All [[Neo Print]]s
|[[File:NEO-SDR_pinout.png|x128px|center]]
|-
|-
|[[File:cd2_sft.jpg|x128px|center]]
|[[File:cd2_sft.jpg|x128px|center]]
|[[NEO-SFT]]
|[[NEO-SFT]] (Fujitsu)
|Graphics related
|Graphics related
|All CD1, all CD2
|All CD1, all CD2
Line 179: Line 206:
|-
|-
|[[File:cd2_voc.jpg|x128px|center]]
|[[File:cd2_voc.jpg|x128px|center]]
|[[NEO-VOC]]
|[[NEO-VOC]] (Yamaha)
|PCM memory handler
|PCM memory handler
|All CD1, all CD2
|All CD1, all CD2
Line 185: Line 212:
|-
|-
|[[File:cd2_ysa.jpg|x128px|center]]
|[[File:cd2_ysa.jpg|x128px|center]]
|[[NEO-YSA]]
|[[NEO-YSA]] (Yamaha)
|Audio subsystem chip
|Audio subsystem chip
|Some
|Some CD2
|
|
|-
|-
|[[File:brd_ysa2.jpg|x128px|center]]
|[[File:brd_ysa2.jpg|x128px|center]]
|[[NEO-YSA2]]
|[[NEO-YSA2]] (Yamaha)
|Audio subsystem chip
|Complete audio subsystem chip and controller inputs
|All CDZ ?, All ROM-only
*Embedded Z80+RAM
|
*Embedded YM2610
|Some MVS, CDZ, All ROM-only
|[[File:NEO-YSA2_pinout.png|x128px|center]]
|-
|-
|[[File:crt_zmc.jpg|x128px|center]]
|[[File:crt_zmc.jpg|x128px|center]]
|[[NEO-ZMC]] (SOIC24)
|[[NEO-ZMC]]
|Z80 Memory Controller
|Z80 Memory Controller
|
|Cartridges
|[[File:neo-zmc_pinout.png|x128px|center]]
|[[File:NEO-ZMC_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_zmc2.jpg|x128px|center]]
|[[File:mvs_zmc2.jpg|x128px|center]]
|[[NEO-ZMC2]] (QFP80R)
|[[NEO-ZMC2]]
|
|
*Z80 Memory Controller
*Z80 Memory Controller
*Sprite tile serializer
*Sprite tile serializer
|Some AES carts, some MVS
|AES carts, some MVS
|[[File:neo-zmc2_pinout.png|x128px|center]]
|[[File:NEO-ZMC2_pinout.png|x128px|center]]
|-
|-
|[[File:crt_pcm.jpg|x128px|center]]
|[[File:crt_pcm.jpg|x128px|center]]
|[[PCM]] (QFP80R)
|[[PCM]]
|
|
*ADPCM bus latches
*ADPCM bus latches
*[[V ROM]] multiplexer
*[[V ROM]] multiplexer
|
|Cartridges
|[[File:pcm_pinout.png|x128px|center]]
|[[File:PCM_pinout.png|x128px|center]]
|-
|-
|[[File:pstg-snk.jpg|x128px|center]]
|[[File:pstg-snk.jpg|x128px|center]]
Line 226: Line 255:
|-
|-
|[[File:mvs_pro-b0.jpg|x128px|center]]
|[[File:mvs_pro-b0.jpg|x128px|center]]
|[[PRO-B0]] (QFP136)
|[[PRO-B0]]
|First generation
|First generation
*Palette arbiter
*Palette arbiter
*Z80 latch
*Z80 latch
|Some AES, some MVS
|Some AES, some MVS
|
|[[File:PRO-B0_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_pro-c0.jpg|x128px|center]]
|[[File:mvs_pro-c0.jpg|x128px|center]]
|[[PRO-C0]] (QFP136)
|[[PRO-C0]]
|First generation
|First generation
*Address decoder
*Address decoder
Line 241: Line 270:
*Palette arbiter
*Palette arbiter
|Some AES, some MVS
|Some AES, some MVS
|
|[[File:PRO-C0_pinout.png|x128px|center]]
|-
|-
|[[File:mvs_pro-ct0.jpg|x64px|center]]
|[[File:mvs_pro-ct0.jpg|x64px|center]]
|[[PRO-CT0]] (SDIP64)
|[[PRO-CT0]]
|[[C ROM]] character serializer and multiplexer
|[[C ROM]] character serializer and multiplexer
|Some AES carts, some MVS
|Some AES carts, some MVS
Line 250: Line 279:
|-
|-
|[[File:brd_pvc.jpg|x128px|center]]
|[[File:brd_pvc.jpg|x128px|center]]
|[[NEO-PVC]]
|[[NEO-PVC]] (Fujitsu)
|[[P ROM]] decryption chip
|[[P ROM]] decryption chip
|
|
Line 261: Line 290:
|
|
|}
|}


=Other chips=
=Other chips=
Line 278: Line 306:
|-
|-
|[[File:aes_68k.jpg|x128px|center]]
|[[File:aes_68k.jpg|x128px|center]]
|[[68k|68HC000]] (DIP64)
|[[68k|68HC000]] (Toshiba DIP64)
|rowspan="2"|16bit CPU  
|rowspan="2"|16bit CPU  
|All
|All
Line 287: Line 315:
|-
|-
|[[File:cd2_68k.jpg|x128px|center]]
|[[File:cd2_68k.jpg|x128px|center]]
|[[68k|68HC000]] (PLCC68)
|[[68k|68HC000]] (Motorola PLCC68)
|
|
|Some
|Some
Line 312: Line 340:
|-
|-
|[[File:crt_hd6301.jpg|x128px|center]]
|[[File:crt_hd6301.jpg|x128px|center]]
|[[HD6301]] (DIP40)
|Hitachi [[HD6301]] (DIP40)
|Microcontroller
|Microcontroller
|colspan="5"|[[Multiplayer]] cartridges
|colspan="5"|[[Multiplayer]] cartridges
Line 353: Line 381:
|-
|-
|[[File:mvs_upd4990.jpg|x128px|center]]
|[[File:mvs_upd4990.jpg|x128px|center]]
|Nec [[UPD4990]]
|NEC [[UPD4990]]
|Real Time Clock
|Real Time Clock
|
|
Line 380: Line 408:
|-
|-
|[[File:aes_z80.jpg|x128px|center]]
|[[File:aes_z80.jpg|x128px|center]]
|[[z80]] (DIP40)
|Zilog [[z80]] (DIP40)
|rowspan="2"|8bit CPU
|rowspan="2"|8bit CPU
|All
|All
Line 389: Line 417:
|-
|-
|[[File:cd2_z80.jpg|x128px|center]]
|[[File:cd2_z80.jpg|x128px|center]]
|[[z80]] (SOIC)
|Toshiba [[z80]] (SOIC)
|
|
|Some
|Some
Line 421: Line 449:
|-
|-
|[[File:mvs_sfix.jpg|x128px|center]]
|[[File:mvs_sfix.jpg|x128px|center]]
|[[SFIX]]
|[[SFIX ROM]]
|Embedded [[Fix layer|Fix]] ROM
|Embedded [[Fix layer|Fix]] ROM
|-
|-

Latest revision as of 06:58, 27 July 2023

Todo:

Picture Reference Description Found in Pinout
LSPC-A0 First generation graphics chip Some AES, some MVS
LSPC2-A2 Second generation graphics chip Some AES, some MVS
LSPC2-A3 Revision of the second generation graphics chip Some MVS
NEO-244 Some MVS
NEO-253 Quint 74HC253, 4-to-1 multiplexers Some MVS
NEO-257 Quad 74HC257, 2-to-1 multiplexers Some MVS
NEO-273 C and S ROM address latches Cartridges
NEO-B1 Second generation graphics chip
  • Sprite and FIX multiplexer
  • Line buffers
  • Palette arbiter
 Some AES, some MVS
NEO-BUF Dual 8-bit bidirectional buffer CD1, CD2, some late MVS
NEO-C1
  • Address decoder
  • Joystick inputs
  • Z80 interface
 Some AES, some MVS
NEO-D0
  • Audio subsystem controller
  • Output port
  • Memory card bankswitching
 All AES ?, some MVS
NEO-CMC
  • NEO-273 logic
  • NEO-ZMC logic
  • NEO-ZMC2 logic
  • C+S ROM decryption
  • C/S ROM multiplexer
  • S ROM bankswitching
  • M ROM decryption (NEOCMC50 only)
  • M ROM bankswitching
 Some AES, some MVS
NEO-DCR-T Some MVS
NEO-E0
  • Vector table swapping
  • Buffer/driver
 Some AES, some MVS
NEO-F0
  • Calendar access
  • Dip/cab switches, coin counters
  • LED marquee outputs
  • Slot selection
 Some MVS
NEO-G0

Quad 245 bidirectional buffer.

  • Palette data buffer
  • Memory card data buffer
  • 68k data bus buffer
 All AES, some MVS ?
NEO-GRC Graphics chip All CD1, all CD2
NEO-GRC2-F (Fujitsu) Graphics chip All CDZ ?, Some MVS
NEO-GRZ (Fujitsu) All-in-one GPU ROM-only
NEO-I0 Multi-purpose MVS specific chip.
  • SFIX ROM address latch
  • Coin counter and lockout outputs
 Some MVS
NEO-MGA
NEO-MGA-T
NEO-MGA-T2 		CD unit interface, latches, address decoding ? All CD1, all CD2, all CDZ, some MVS
NEO-OFC (Fujitsu) Graphics chip All CD1, all CD2
NEO-PCM2 (Fujitsu)
  • PCM
  • P ROM decoding, bankswitching and decryption
 ROM-only boards
NEO-SDR-T
  • Joypad I/O
  • Z80 address and port decoding
  • 68k/Z80 communication latches and interrupt generation
 Some MVS, All Neo Prints
NEO-SFT (Fujitsu) Graphics related All CD1, all CD2
NEO-SUD Z80 subsystem controler All CD1, all CD2
NEO-VOC (Yamaha) PCM memory handler All CD1, all CD2
NEO-YSA (Yamaha) Audio subsystem chip Some CD2
NEO-YSA2 (Yamaha) Complete audio subsystem chip and controller inputs
  • Embedded Z80+RAM
  • Embedded YM2610
 Some MVS, CDZ, All ROM-only
NEO-ZMC Z80 Memory Controller Cartridges
NEO-ZMC2
  • Z80 Memory Controller
  • Sprite tile serializer
 AES carts, some MVS
PCM
  • ADPCM bus latches
  • V ROM multiplexer
 Cartridges
PSTG-SNK

Neo Print GPU.

PRO-B0 First generation
  • Palette arbiter
  • Z80 latch
 Some AES, some MVS
PRO-C0 First generation
  • Address decoder
  • Glue
  • Line buffer
  • Palette arbiter
 Some AES, some MVS
PRO-CT0 C ROM character serializer and multiplexer Some AES carts, some MVS
NEO-PVC (Fujitsu) P ROM decryption chip
NEO-SMA P ROM decryption chip

Other chips

Picture Reference Description Found in
AES MVS CD1 CD2 CDZ
68HC000 (Toshiba DIP64) 16bit CPU All Some
68HC000 (Motorola PLCC68) Some All All All
Sony CXA1145 RGB encoder All
Sony CXA1645 ? All ?
Hitachi HD6301 (DIP40) Microcontroller Multiplayer cartridges
Sanyo LC78815 Stereo DAC ? All
Sanyo LC89515 CD host and error corrector All All ?
Sanyo LC8953 PUPPET All Some ?
Sanyo LC98000 PUPPET replacement Some ?
NEC UPD4990 Real Time Clock All
Yamaha YM2610 Sound synthesizer All All All Some
Yamaha YM3016 Audio DAC All All All Some
Zilog z80 (DIP40) 8bit CPU All Some
Toshiba z80 (SOIC) Some All All All


Memory chips

Picture Reference Description Found in
LO Shrink lookup ROM All systems
SP-S2 MVS System ROM MVS systems
SM1 Embedded sound driver ROM
SFIX ROM Embedded Fix ROM
NEO-EP0 AES System ROM AES systems
Picture needed TOP-SP1-1 CD2 System ROM Top loading CD systems (LC8953 versions)
Picture needed TOP-SP1-2 CD2 System ROM Top loading CD systems (LC98000 versions)
FRONT-SP1 CD1 System ROM Front loading CD systems

Subcategories

This category has only the following subcategory.

C

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