Memory mapped registers: Difference between revisions

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Decode masks aren't verified !
Decode masks aren't verified !


Decode masks are used to know which register will be mapped to a precise address, they can be seen as a sort of mirroring range notation.
Decode masks are used to know which register will be mapped to a given address, they can be seen as a sort of mirroring range notation.


A "1" bit means that the corresponding address line is involved in decoding, a "0" bit means it can be anything.
A "1" bit means that the corresponding address bit is involved in decoding, a "0" means it's ignored.


For example, {{Reg|REG_P1CNT}}'s base is $300000 and its mask is $FE0001:
For example, {{Reg|REG_P1CNT}}'s base is $300000 and its mask is $FE0001:
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</pre>
</pre>


This means that it should also be accessible at $300002, $300004, $300006... up to $31FFFE. The highest address is BASE OR (NOT MASK).
This means that it's also accessible at $300002, $300004, $300006... up to $31FFFE. The highest address is BASE OR (NOT MASK).


==Mirror guesser==
==Mirror guesser==
Line 22: Line 22:
<div id="mirror-guesser"></div>
<div id="mirror-guesser"></div>
<div id="mguessresult"></div>
<div id="mguessresult"></div>


=Register descriptions=
=Register descriptions=
Line 52: Line 51:
|'''Write'''
|'''Write'''
|-
|-
|[[Hardware DIPs]] (active low) {{8BitRegister|Freeze|1|Freeplay|1|Enable [[Multiplayer]]|1|Comm. ID code|2|0:Normal controller<br>1:Mahjong keyboard|1|0:1 chute<br>1:2 chutes|1|Settings mode|1}}
|[[Hardware DIPs]] (active low) {{8BitRegister|Freeze game|1|Freeplay|1|Enable [[Multiplayer]]|1|Multiplayer ID code|2|0:Normal controller<br>1:Mahjong keyboard|1|0:1 coin chute<br>1:2 coin chutes|1|Settings mode|1}}
|Kick [[watchdog]]
|Kick [[watchdog]]
|}
|}
Line 69: Line 68:
|'''Write'''
|'''Write'''
|-
|-
|{{8BitRegister|[[Test button]]|1|[[NEO-F0|Type]]|1|?|6}}
|{{8BitRegister|[[Test button]]|1|[[NEO-F0|Type]]<br/>0: 2 slots<br/>1: 4 or 6 slots|1|?|6}}
|?
|?
|}
|}
Line 141: Line 140:
|'''Write'''
|'''Write'''
|-
|-
|Aux inputs (active low)
|Aux inputs (lower bits active low)
{{8BitRegister|0:AES<br>1:MVS|1|[[Memory card]]<br>write protected|1|Memory card<br>inserted if 00|2|Select P2|1|Start P2|1|Select P1|1|Start P1|1|}}
{{8BitRegister|0:AES<br>1:MVS|1|[[Memory card]]<br>write protected if 1|1|Memory card<br>inserted if 00|2|Select P2|1|Start P2|1|Select P1|1|Start P1|1|}}
|?
|?
|}
|}
Line 231: Line 230:
|-
|-
|?
|?
|8-bit data for LEDs and [[marquee]]. See [[MV-LED]].
|8-bit data for credits displays and the [[marquee]]. See [[MV-LED]].
|}
|}


Line 393: Line 392:
==System registers==
==System registers==


Handled by a 74HC259 addressable latch on cart systems. Byte writes only. Decode mask: $FE0001. Registers go in pairs, bit 4 of address is the data bit.
Data written doesn't matter. Odd byte writes only. Decode mask: $FE0001.
 
Registers go in pairs, bit 4 of the address is actually the data bit.
 
Handled by a 74HC259 addressable latch on cart systems.  


{| class="regdef"
{| class="regdef"
Line 418: Line 421:
|$3A0005
|$3A0005
|REG_CRDUNLOCK1
|REG_CRDUNLOCK1
|Enable writes to memory card (use REG_CRDUNLOCK2 too)
|Enable writes to [[memory card]] (unused in CD systems)
|-
|-
|$3A0015
|$3A0015
|REG_CRDLOCK1
|REG_CRDLOCK1
|Disable writes to [[memory card]]
|Disable writes to memory card (unused in CD systems)
|-
|-
|$3A0007
|$3A0007
|REG_CRDLOCK2
|REG_CRDLOCK2
|Disable writes to memory card
|Disable writes to memory card (unused in CD systems)
|-
|-
|$3A0017
|$3A0017
|REG_CRDUNLOCK2
|REG_CRDUNLOCK2
|Enable writes to memory card (use REG_CRDUNLOCK1 too)  
|Enable writes to memory card (unused in CD systems)
|-
|-
|$3A0009
|$3A0009
Line 467: Line 470:
==Video registers==
==Video registers==


Handled by the [[GPU]]s. Byte writes only work on even addresses and stores the same data in the MSB and LSB. Odd addresses aren't mapped ? Decode mask: $FE0001.
Handled by the [[LSPC]]. Byte writes are only effective on even addresses and they store the same data in both bytes. Odd addresses aren't mapped ? Decode mask: $FE0001.


{| class="regdef"
{| class="regdef"
Line 477: Line 480:
|$3C0000
|$3C0000
|REG_VRAMADDR
|REG_VRAMADDR
|Read [[VRAM]] (address isn't changed)
|Read from [[VRAM]] (address doesn't change)
|Sets VRAM address
|Sets VRAM address
|-
|-
|$3C0002
|$3C0002
|REG_VRAMRW
|REG_VRAMRW
|Read VRAM (address isn't changed)
|Read from VRAM (address doesn't change)
|Write VRAM
|Write to VRAM (modulo is applied after)
|-
|-
|$3C0004
|$3C0004
|REG_VRAMMOD
|REG_VRAMMOD
|Reads VRAM address modulo
|Reads VRAM address modulo
|Sets VRAM address modulo (signed)
|Sets VRAM address modulo
|-
|-
|$3C0006
|$3C0006
|REG_LSPCMODE
|REG_LSPCMODE
|{{16BitRegister|Raster line counter.<br>See [[Display timing]]|9|-|3|1:50Hz<br>0:60Hz ([[GPU|LSPC2]] only)|1|[[Auto animation]] counter|3}}
|{{16BitRegister|Raster line counter.<br>See [[Display_timing#Vertical|Display timing]]|9|0|3|1:50Hz<br>0:60Hz ([[GPU|LSPC2]] only)|1|[[Auto animation]] counter|3}}
|{{16BitRegister|Auto animation speed<br>(in frames)|8|[[Timer interrupt]]<br>mode|3|Timer interrupt enable|1|Disable auto animation|1|?|3}}
|{{16BitRegister|Auto animation speed<br>(in frames)|8|[[Timer interrupt]]<br>mode|3|Timer interrupt enable|1|Disable auto animation|1|Unused|3}}
Reset value: ????????00000---
|-
|-
|$3C0008
|$3C0008
|REG_TIMERHIGH
|REG_TIMERHIGH
|Like REG_VRAMADDR.
|Like REG_VRAMADDR.
|MSBs of timer reload value.
|16 highest bits of the [[timer interrupt|timer]] reload value.
|-
|-
|$3C000A
|$3C000A
|REG_TIMERLOW
|REG_TIMERLOW
|Like REG_VRAMRW.
|Like REG_VRAMRW.
|LSBs of timer reload value.
|16 lowest bits of the timer reload value.
|-
|-
|$3C000C
|$3C000C
|REG_IRQACK
|REG_IRQACK
|Like REG_VRAMMOD.
|Like REG_VRAMMOD.
|Interrupt Acknowledge (byte !).
|[[68k interrupts|Interrupt]] acknowledge.
{{8BitRegister|?|5|Ack VBlank|1|Ack HBlank|1|Ack IRQ3|1}}
{{8BitRegister|Unused|5|Ack VBlank IRQ|1|Ack timer IRQ|1|Ack IRQ3|1}}
|-
|-
|$3C000E
|$3C000E
Line 516: Line 520:
|Bit 0=1: Stops timer counter during first and last 16 lines (32 total) when in PAL mode.
|Bit 0=1: Stops timer counter during first and last 16 lines (32 total) when in PAL mode.
|}
|}


==NeoGeo CD registers==
==NeoGeo CD registers==
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|REG_CDDINPUT
|REG_CDDINPUT
|Byte
|Byte
|{{8BitRegister|?|3|CDCK input|1|4-bit bus from the [[CD drive]]|4}}
|{{8BitRegister|-|3|CDCK input|1|4-bit bus from the [[CD drive]]|4}}
|?
|?
|[[NEO-MGA]]
|[[NEO-MGA]]
Line 543: Line 546:
|Byte
|Byte
|?
|?
|4-bit bus to the CD drive
|{{8BitRegister|-|4|4-bit bus to the [[CD drive]]|4}}
|[[NEO-MGA]]
|[[NEO-MGA]]
|-
|-
Line 550: Line 553:
|Byte
|Byte
|?
|?
|{{8BitRegister|?|6|Bus direction ?<br>0:Input<br>1:Output|1|HOCK output}}
|{{8BitRegister|-|4|Must be 0|2|Signal selection<br>0:4-bit bus direction<br>1:HOCK output|1|State<br>Dir:0:Out 1:In<br>HOCK:0:Low 1:High|1}}
|[[NEO-MGA]]
|-
|$FF0167
|REG_CDDSTAT
|Byte
|[[CD drive]] status lines.{{8BitRegister|-|3|MUTE|1|SBSO|1|SCOR|1|WFCK|1|EXCK|1}}
|{{8BitRegister|-|7|EXCK|1}}
|[[NEO-MGA]]
|[[NEO-MGA]]
|}
|}
Line 581: Line 591:
|Byte
|Byte
|?
|?
|Video output. 1=Enable 0=Disable
|1=Enable 0=Disable video output.
|}
|}


Line 598: Line 608:
|Byte
|Byte
|?
|?
|Upload zone 1MiB SPR DRAM bank selection
|Upload zone 1MiB SPR DRAM bank selection (2 LSBs).
|?
|?
|-
|-
Line 605: Line 615:
|Byte
|Byte
|?
|?
|Upload zone 512KiB PCM DRAM bank selection
|Upload zone 512KiB PCM DRAM bank selection (1 LSB).
|?
|?
|-
|-
Line 706: Line 716:
|}
|}


===Unkown===
===Misc===


{| class="regdef"
{| class="regdef"
Line 720: Line 730:
|Word
|Word
|?
|?
|NeoRaine load_files, really interrupt mask ?
|Enables Vector 22 interrupts. NeoRaine calls load_files.
|?
|rowspan="8"|[[LC8953]]
|-
|-
|$FF0004
|$FF0004
Line 728: Line 738:
|?
|?
|CDM3-2 BIOS writes 0,1,3,7
|CDM3-2 BIOS writes 0,1,3,7
|?
|-
|-
|$FF0006
|$FF0006
Line 735: Line 744:
|?
|?
|CDM3-2 BIOS writes 0x71FF, CDZ writes 0x71FF
|CDM3-2 BIOS writes 0x71FF, CDZ writes 0x71FF
|?
|-
|-
|$FF0008
|$FF0008
Line 742: Line 750:
|?
|?
|CDM3-2 BIOS writes 0x0000, CDZ writes 0x0000
|CDM3-2 BIOS writes 0x0000, CDZ writes 0x0000
|?
|-
|-
|$FF000A
|$FF000A
Line 749: Line 756:
|?
|?
|CDM3-2 BIOS writes 0x7E40, CDZ writes 0x7E00
|CDM3-2 BIOS writes 0x7E40, CDZ writes 0x7E00
|?
|-
|-
|$FF000E
|$FF000C
|?
|?
|Byte
|Word
|?
|CDM3-2 BIOS writes $3F,$3C
|?
|?
|Read and stored on vector 23 interrupt.
|-
|-
|$FF000F
|$FF000F
Line 762: Line 767:
|Byte
|Byte
|?
|?
|NeoCDIRQUpdate(byteValue);
|[[68k interrupts|Interrupt]] acknowledge.
CDM3-2 BIOS writes $20,$10,$08,$04
{{8BitRegister|?|2|Vector 21|1|Vector 22|1|Vector 23|1|?|3}}
|?
|-
|-
|$FF0011
|$FF0010/11
|?
|?
|Byte
|Byte
|?
|?
|CDM3-2 BIOS writes $FE
|CDM3-2 BIOS writes $FE
|?
|-
|-
|$FF0017
|$FF0017
|?
|?
|Byte
|Byte
|colspan="2"|nNeoCDMode
|colspan="2"|CD mode, maybe CDDA mute ? Bit 0: 0=Audio 1=Data.
CDM3-2 BIOS read/writes bit 0
|?
|?
|-
|-
Line 783: Line 785:
|?
|?
|Byte
|Byte
|colspan="2"|nLC8951Register (4 LSB)
|colspan="2"|LC8951 register address (4 LSB)
CDM3-2 BIOS writes low nibble
|rowspan="2"|[[LC89515]]
|[[LC8951]]
|-
|-
|$FF0103
|$FF0103
|?
|?
|Byte
|Byte
|colspan="2"|nLC8951Register value
|colspan="2"|LC8951 register  value
CDM3-2 BIOS writes 0x10, CDZ writes 0x00 (start up init)
|[[LC8951]]
|-
|-
|$FF0105
|$FF0105
|?
|REG_TRANSAREA
|Byte
|Byte
|?
|?
|nActiveTransferArea = byteValue
|Set active transfer area
upload_type_w
*0:Sprites
*1:ADPCM
*4:Z80
*5:Fix
|?
|?
|-
|-
Line 828: Line 830:
|?
|?
|MapVectorTable(!(byteValue == 0xFF));
|MapVectorTable(!(byteValue == 0xFF));
|?
|rowspan="4"|[[NEO-MGA]]
|-
|-
|$FF016F
|$FF016F
|REG_DISBLIRQ
|REG_UPLOAD_EN
|Byte
|Byte
|?
|?
|Disable/enable interrupts nTransferWriteEnable = byteValue
|Enable/disable writes to the [[68k memory map|upload zone]] ($E00000)
|?
|-
|-
|$FF0181
|$FF0181
|REG_CDRST
|REG_CDIRQ_EN
|Byte
|Byte
|?
|?
|[[CD drive]] /RESET
|Bit 0: Enable CD drive interrupt
|?
|-
|-
|$FF0183
|$FF0183
Line 849: Line 849:
|?
|?
|Active-low Z80 RESET ($0/$FF)
|Active-low Z80 RESET ($0/$FF)
|[[NEO-MGA]] ?
|}
|}


Latest revision as of 08:55, 9 October 2023


Address decode masks

Decode masks aren't verified !

Decode masks are used to know which register will be mapped to a given address, they can be seen as a sort of mirroring range notation.

A "1" bit means that the corresponding address bit is involved in decoding, a "0" means it's ignored.

For example, REG_P1CNT's base is $300000 and its mask is $FE0001: 

BASE 00110000 00000000 00000000
MASK 11111110 00000000 00000001
     0011000x xxxxxxxx xxxxxxx0

This means that it's also accessible at $300002, $300004, $300006... up to $31FFFE. The highest address is BASE OR (NOT MASK).

Mirror guesser

Register descriptions

I/O registers

REG_P1CNT

Read Write
Joypad port 1 inputs (active low)
Bit 7 6 5 4 3 2 1 0
Def D CBARightLeftDownUp
?
  • Address: $300000
  • Decode mask: $FE0001
  • Handled by: NEO-C1


REG_DIPSW

Read Write
Hardware DIPs (active low)
Bit 7 6 5 4 3 2 1 0
Def Freeze game FreeplayEnable MultiplayerMultiplayer ID code0:Normal controller
1:Mahjong keyboard		0:1 coin chute
1:2 coin chutes		Settings mode
Kick watchdog
  • Address: $300001
  • Decode mask: $FE0081 (not sure for write)
  • Handled by: NEO-F0 (read), NEO-B1 (write)


REG_SYSTYPE

Read Write
Bit 7 6 5 4 3 2 1 0
Def Test button Type
0: 2 slots
1: 4 or 6 slots		?
?

Reads the unused DSW2 on MV4 boards. Used for system ID on other boards.

  • Address: $300081
  • Decode mask: $FE0081
  • Handled by: NEO-F0


REG_SOUND

Read Write
Read Z80 reply code Send command to Z80
  • Address: $320000
  • Decode mask: $FE0001
  • Handled by: NEO-C1


REG_STATUS_A

Read Write
Switch inputs are active low
Bit 7 6 5 4 3 2 1 0
Def RTC data bit RTC time pulse0:4-SLOT
1:6-SLOT		Coin-in 4Coin-in 3Service buttonCoin-in 2Coin-in 1
?
  • Address: $320001
  • Decode mask: $FE0001
  • Handled by: NEO-F0


REG_P2CNT

Read Write
Joypad port 2 inputs (active low)
Bit 7 6 5 4 3 2 1 0
Def D CBARightLeftDownUp
?
  • Address: $340000
  • Decode mask: $FE0001
  • Handled by: NEO-C1


REG_STATUS_B

Read Write
Aux inputs (lower bits active low)
Bit 7 6 5 4 3 2 1 0
Def 0:AES
1:MVS		 Memory card
write protected if 1		Memory card
inserted if 00		Select P2Start P2Select P1Start P1
?
  • Address: $380000
  • Decode mask: $FE0001
  • Handled by: NEO-C1


REG_POUTPUT

Read Write
? Joypad ports outputs
Bit 7 6 5 4 3 2 1 0
Def ? P2 outputsP1 outputs
  • Address: $380001
  • Decode mask: $FE0071
  • Handled by: NEO-D0


REG_CRDBANK

Read Write
?
Bit 7 6 5 4 3 2 1 0
Def Memory card bank selection
  • Address: $380011
  • Decode mask: $FE0071
  • Handled by: NEO-D0


REG_SLOT

Read Write
?
Bit 7 6 5 4 3 2 1 0
Def ? Slot #

(Mirror of REG_POUTPUT on the AES)

  • Address: $380021
  • Decode mask: $FE00F1
  • Handled by: NEO-F0


REG_LEDLATCHES

Read Write
?
Bit 7 6 5 4 3 2 1 0
Def ? Latch LED2 dataLatch LED1 dataLatch marquee data?

LED data is latched on 1 to 0 transition.

  • Address: $380031
  • Decode mask: $FE00F1
  • Handled by: NEO-F0


REG_LEDDATA

Read Write
? 8-bit data for credits displays and the marquee. See MV-LED.
  • Address: $380041
  • Decode mask: $FE00F1
  • Handled by: NEO-F0


REG_RTCCTRL

Read Write
? MAME upd4990a_control_16_w
Bit 7 6 5 4 3 2 1 0
Def RTC StrobeRTC ClockRTC DIN
  • Address: $380051
  • Decode mask: $FE00F1
  • Handled by: NEO-F0


REG_RESETCC1

Read Write
? Any, coin counter 1 floats
  • Address: $380061
  • Decode mask: $FE00F1
  • Handled by: NEO-I0


REG_RESETCC2

Read Write
? Any, coin counter 2 floats
  • Address: $380063
  • Decode mask: $FE00F1
  • Handled by: NEO-I0


REG_RESETCL1

Read Write
? Any, coin lockout 1 floats
  • Address: $380065
  • Decode mask: $FE00F1
  • Handled by: NEO-I0


REG_RESETCL2

Read Write
? Any, coin lockout 2 floats
  • Address: $380067
  • Decode mask: $FE00F1
  • Handled by: NEO-I0


REG_SETCC1

Read Write
? Any, coin counter 1 sinks current
  • Address: $3800E1
  • Decode mask: $FE00F1
  • Handled by: NEO-I0


REG_SETCC2

Read Write
? Any, coin counter 2 sinks current
  • Address: $3800E3
  • Decode mask: $FE00F1
  • Handled by: NEO-I0


REG_SETCL1

Read Write
? Any, coin lockout 1 sinks current
  • Address: $3800E5
  • Decode mask: $FE00F1
  • Handled by: NEO-I0


REG_SETCL2

Read Write
? Any, coin lockout 2 sinks current
  • Address: $3800E7
  • Decode mask: $FE00F1
  • Handled by: NEO-I0

System registers

Data written doesn't matter. Odd byte writes only. Decode mask: $FE0001.

Registers go in pairs, bit 4 of the address is actually the data bit.

Handled by a 74HC259 addressable latch on cart systems.

Address Name Write
$3A0001 REG_NOSHADOW Normal video output
$3A0011 REG_SHADOW Darken video output
$3A0003 REG_SWPBIOS BIOS vector table
$3A0013 REG_SWPROM Use the cart's vector table
$3A0005 REG_CRDUNLOCK1 Enable writes to memory card (unused in CD systems)
$3A0015 REG_CRDLOCK1 Disable writes to memory card (unused in CD systems)
$3A0007 REG_CRDLOCK2 Disable writes to memory card (unused in CD systems)
$3A0017 REG_CRDUNLOCK2 Enable writes to memory card (unused in CD systems)
$3A0009 REG_CRDREGSEL Enable "Register select" for memory card
$3A0019 REG_CRDNORMAL Disable "Register select" for memory card
$3A000B REG_BRDFIX Use the embedded SFIX ROM and SM1 ROM
$3A001B REG_CRTFIX Use the cart's S ROM and M1 ROM
$3A000D REG_SRAMLOCK Write-protects backup RAM (MVS)
$3A001D REG_SRAMUNLOCK Unprotects backup RAM (MVS)
$3A000F REG_PALBANK1 Use palette bank 1
$3A001F REG_PALBANK0 Use palette bank 0

Video registers

Handled by the LSPC. Byte writes are only effective on even addresses and they store the same data in both bytes. Odd addresses aren't mapped ? Decode mask: $FE0001.

Address Name Read Write
$3C0000 REG_VRAMADDR Read from VRAM (address doesn't change) Sets VRAM address
$3C0002 REG_VRAMRW Read from VRAM (address doesn't change) Write to VRAM (modulo is applied after)
$3C0004 REG_VRAMMOD Reads VRAM address modulo Sets VRAM address modulo
$3C0006 REG_LSPCMODE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def Raster line counter.
See Display timing		 01:50Hz
0:60Hz (LSPC2 only)		Auto animation counter
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def Auto animation speed
(in frames)		 Timer interrupt
mode		Timer interrupt enableDisable auto animationUnused

Reset value: ????????00000---

$3C0008 REG_TIMERHIGH Like REG_VRAMADDR. 16 highest bits of the timer reload value.
$3C000A REG_TIMERLOW Like REG_VRAMRW. 16 lowest bits of the timer reload value.
$3C000C REG_IRQACK Like REG_VRAMMOD. Interrupt acknowledge.
Bit 7 6 5 4 3 2 1 0
Def Unused Ack VBlank IRQAck timer IRQAck IRQ3
$3C000E REG_TIMERSTOP Like REG_LSPCMODE. Bit 0=1: Stops timer counter during first and last 16 lines (32 total) when in PAL mode.

NeoGeo CD registers

NEO-MGA / LC8953 / LC98000 ?

CD drive

Address Name Size Read Write Handled by
$FF0161 REG_CDDINPUT Byte
Bit 7 6 5 4 3 2 1 0
Def - CDCK input4-bit bus from the CD drive
? NEO-MGA
$FF0163 REG_CDDOUTPUT Byte ?
Bit 7 6 5 4 3 2 1 0
Def - 4-bit bus to the CD drive
NEO-MGA
$FF0165 REG_CDDCTRL Byte ?
Bit 7 6 5 4 3 2 1 0
Def - Must be 0Signal selection
0:4-bit bus direction
1:HOCK output		State
Dir:0:Out 1:In
HOCK:0:Low 1:High
NEO-MGA
$FF0167 REG_CDDSTAT Byte CD drive status lines.
Bit 7 6 5 4 3 2 1 0
Def - MUTESBSOSCORWFCKEXCK
Bit 7 6 5 4 3 2 1 0
Def - EXCK
NEO-MGA

Video

Address Name Size Read Write Handled by
$FF0111 REG_DISBLSPR Byte ? 1=Disable 0=Enable sprites NEO-GRC/NEO-OFC
$FF0115 REG_DISBLFIX Byte ? 1=Disable 0=Enable fix layer
$FF0119 REG_ENVIDEO Byte ? 1=Enable 0=Disable video output.

Memory

Address Name Size Read Write Handled by
$FF01A1 REG_SPRBANK Byte ? Upload zone 1MiB SPR DRAM bank selection (2 LSBs). ?
$FF01A3 REG_PCMBANK Byte ? Upload zone 512KiB PCM DRAM bank selection (1 LSB). ?
$FF01A7 REG_???BANK Byte ? $A00000 zone bank number. What is this ? ?
$FF0121 REG_UPMAPSPR Byte ? NeoSetSpriteSlot(1);

Set upload zone to SPR DRAM

?
$FF0123 REG_UPMAPPCM Set upload zone to PCM DRAM
$FF0127 REG_UPMAPZ80 Set upload zone to Z80 DRAM
$FF0129 REG_UPMAPFIX Set upload zone to FIX DRAM
$FF0141 REG_UPUNMAPSPR Unset SPR DRAM to upload zone
$FF0143 REG_UPUNMAPPCM Unset PCM DRAM to upload zone
$FF0147 REG_UPUNMAPZ80 Unset Z80 DRAM to upload zone
$FF0149 REG_UPUNMAPFIX Unset FIX DRAM to upload zone

DMA

Address Name Size Read Write Handled by
$FF0061 ? Byte ? Bit 6: Execute DMA microcode LC8953
$FF0064~$FF0067 REG_DMA_ADDR1 Longword ? Sets DMA source address.
$FF0068~$FF006B REG_DMA_ADDR2 Longword ? Sets DMA destination address.
$FF006C~$FF006F REG_DMA_VALUE Longword ? Sets DMA value for filling.
$FF0070~$FF0073 REG_DMA_COUNT Longword ? Sets DMA length.
$FF007E REG_DMA_MODE Word ? Sets DMA mode.
$FF007E~$FF008E ? Words ? Microcode (16x 9-bit opcodes)

Misc

Address Name Size Read Write Handled by
$FF0002 ? Word ? Enables Vector 22 interrupts. NeoRaine calls load_files. LC8953
$FF0004 ? Word ? CDM3-2 BIOS writes 0,1,3,7
$FF0006 ? Word ? CDM3-2 BIOS writes 0x71FF, CDZ writes 0x71FF
$FF0008 ? Word ? CDM3-2 BIOS writes 0x0000, CDZ writes 0x0000
$FF000A ? Word ? CDM3-2 BIOS writes 0x7E40, CDZ writes 0x7E00
$FF000C ? Word ? Read and stored on vector 23 interrupt.
$FF000F ? Byte ? Interrupt acknowledge.
Bit 7 6 5 4 3 2 1 0
Def ? Vector 21Vector 22Vector 23?
$FF0010/11 ? Byte ? CDM3-2 BIOS writes $FE
$FF0017 ? Byte CD mode, maybe CDDA mute ? Bit 0: 0=Audio 1=Data. ?
$FF0101 ? Byte LC8951 register address (4 LSB) LC89515
$FF0103 ? Byte LC8951 register value
$FF0105 REG_TRANSAREA Byte ? Set active transfer area
  • 0:Sprites
  • 1:ADPCM
  • 4:Z80
  • 5:Fix
 ?
$FF0108 ? Word ? CDM3-2 BIOS writes $5555 ?
$FF010C ? Word ? CDM3-2 BIOS writes $5555 and reads ?
$FF011C REG_CDCONFIG Word
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def 1 CD Mech
0:TOP/CDZ
1:FRONT		Lid Status
(Opposite on CDZ)		Configuration
jumpers		?
? NEO-CDD board
$FF016D Byte ? MapVectorTable(!(byteValue == 0xFF)); NEO-MGA
$FF016F REG_UPLOAD_EN Byte ? Enable/disable writes to the upload zone ($E00000)
$FF0181 REG_CDIRQ_EN Byte ? Bit 0: Enable CD drive interrupt
$FF0183 REG_Z80RST Byte ? Active-low Z80 RESET ($0/$FF)

CDDA

Address Name Size Read Write Handled by
$FF0188 REG_CDDALEFTL Word See Reading CDDA sound levels No effect NEO-MGA
$FF018A REG_CDDARIGHTL
$FF01FC ? Word ? CDDA control ? ?
$FF01FE ? Word ? CD music/data switch ? ?
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